Design of a CMOS Compatible CFOA and its Application in Analog Filtering

It is presented the design of a current-feedback operational amplifier (CFOA) which is suitable for implementation with standard CMOS integratedcircuit technology of 0.35µm. The characteristics of the CFOA are derived by using biases of ±2.5V and Ibias=20µA. The usefulness of the CFOA is demonstrated by designing mixed-mode biquads which realize the low-pass, high-pass, band-pass, notch and all-pass filter functions. As a result, it is highlighted that the SPICE simulations of the biquad working in voltage-mode are in good agreement with the biquad working in current-mode.     

Low Voltage Rail to Rail CMOS Current Feedback Operational Amplifier and its Applications for Analog VLSI

This paper presents a new CMOS current feedback operational amplifier (CFOA) with rail to rail swing capability at all terminals. The circuit operates as a class AB for lower power consumption. Besides operating at low supply voltages of ±1.5 V, the proposed CFOA has a standby current of 200 A. The proposed CFOA circuit is thus a versatile building block for low voltage low power applications. The applications of the CFOA to realize a transconductor/multiplier cell, MOS-C differential integrator, MOS-C bandpass filter and MOS-C oscillator are given. PSpice simulations based on 1.2 m level three parameters obtained from MOSIS are given.     

New Fully‐Differential CMOS Second‐Generation Current Conveyer

This paper presents a new CMOS fully‐differential second‐generation current conveyor (FDCCII). The proposed FDCCII is based on a fully‐differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit operating at a supply voltage of ± 1.5 V, it has a total standby current of 380 µA. The applications of the FDCCII to realize a variable gain amplifier, fully‐differential integrator, and fully‐differential second‐order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS 0.35 µm technology.     

低电压低功耗CMOS电流反馈运算放大器的设计

设计了一种低压低功耗的电流反馈运算放大器(CFOA),采用了0.18μm CMOS工艺,工作在0.9 V的电源电压下,并给出了Spectre仿真结果,功耗为245μW。输入采用了轨对轨的结构以提高输入电压摆幅,输出采用互补输出结构,使输出工作在甲乙类状态,以降低电路的功耗。     

Rail-supply insensitive CMOS current generator

The theoretical background and a selection of simulated results are presented for a 10?µA PTAT current generator that is a modified CMOS version of an existing bipolar configuration. Using standard 0.35?µm CMOS technology, the circuit exhibits a current variation of less than 0.01% when the supply rail voltage is changed from 0.5 to 10?V.     

Low‐Voltage Current‐Sensing CMOS Interface Circuit for Piezo‐Resistive Pressure Sensor

A new low‐voltage CMOS interface circuit with digital output for piezo‐resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo‐resistance due to applied pressure and to allow low‐voltage circuit operation. A simple 1‐bit first‐order delta‐sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 µm CMOS technology and draws less than 200 µA from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non‐linearity error.     

Low-voltage,wide-range,current-controlled DC current generator

Operating from a 1?V rail supply, a proposed CMOS current-controlled DC current generator can function as a repeater, attenuator or amplifier over the input current range, 1?µA to 1?mA, with a current-transfer ratio accuracy better than 1% using IBM technology, characterised by a process with a 0.13?µm minimum feature size. In repeater mode, the incremental output resistance exceeds 30?MΩ for an output current of 500?µA at an output voltage of 0.20?V, and exceeds 1?MΩ for an output current of 1?mA at an output voltage of 0.22?V. For zero input current, the circuit dissipation is 117?µW.     

New CMOS Fully‐Differential Transconductor and Application to a Fully‐Differential Gm‐C Filter

A new CMOS voltage‐controlled fully‐differential transconductor is presented. The basic structure of the proposed transconductor is based on a four‐MOS transistor cell operating in the triode or saturation region. It achieves a high linearity range of ± 1 V at a 1.5 V supply voltage. The proposed transconductor is used to realize a new fully‐differential Gm‐C low‐pass filter with a minimum number of transconductors and grounded capacitors. PSpice simulation results for the transconductor circuit and its filter application indicating the linearity range and verifying the analytical results using 0.35 μm technology are also given.     

New CMOS realization of high performance Voltage Differencing Inverting Buffered Amplifier and its filter application

This paper describes a high performance voltage differencing inverting buffered amplifier (VDIBA). The transconductance of the proposed circuit is enhanced by using positive feedback technique with only two extra transistors used in active load. Moreover, the bandwidth of proposed circuit is enhanced by using resistive compensation technique. The performance of proposed VDIBA is demonstrated by detailed frequency analysis. Furthermore, it is shown that the transconductance can be enhanced up to 4.61 mS at biasing current of 300 µA. In addition, a third order low pass filter is given as an application example to confirm the high performance of the proposed VDIBA. The proposed low pass filter operates at natural pole frequency of 15 MHz. The proposed VDIBA and its filter application are implemented using TSMC 90 nm CMOS technology in Cadence virtuoso schematic composer at ±0.6 V supply voltage.     

Design of Two‐Stage Class AB CMOS Buffers: A Systematic Approach

A systematic approach for the design of two‐stage class AB CMOS unity‐gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity‐gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 µm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 µW).     

CMOS design of a four-quadrant multiplier based on a novel squarer circuit

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.     

A novel ±0.5 V,high current drive,and rail to rail current operational amplifier

A current operational amplifier (COA) with very high current drive capability is presented in this paper. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high frequency bandwidth, extremely high CMRR, high output impedance, and true rail to rail output voltage swing range while operating at very low power supply of ±0.5 V. The interesting results such as current drive capability of ±1 mA, high output impedance of 5 GΩ, wide gain bandwidth of 220 MHz, extremely high output voltage swing of ±0.45 V, which interestingly provides the highest yet reported output voltage compliance for current mode building blocks implemented by regular CMOS technology, low static power consumption of 159 μW, and very high CMRR of 155 dB is achieved utilizing standard CMOS technology. Full process, voltage, and temperature variation analysis of the circuit is also investigated in order to approve the well robustness of the structure. The transient stepwise and sinusoidal response analysis is also done to verify the proposed COA stability.     

High‐Performance On‐Chip Thermionic Electron Micro‐Emitter Arrays Based on Super‐Aligned Carbon Nanotube Films

An important advancement towards the realization of miniaturized and fully integrated vacuum electronic devices will be the development of on‐chip integrated electron sources with stable and reproducible performances. Here, the fabrication of high‐performance on‐chip thermionic electron micro‐emitter arrays is demonstrated by exploiting suspended super‐aligned carbon nanotube films as thermionic filaments. For single micro‐emitter, an electron emission current up to ≈20 µA and density as high as ≈1.33 A cm^?2 are obtained at a low‐driven voltage of 3.9 V. The turn‐on/off time of a single micro‐emitter is measured to be less than 1 µs. Particularly, stable (±1.2% emission current fluctuation for 30 min) and reproducible (±0.2% driven voltage variation over 27 cycles) electron emission have been experimentally observed under a low vacuum of ≈5 × 10^?4 Pa. Even under a rough vacuum of ≈10^?1 Pa, an impressive reproducibility (±2% driven voltage variation over 20 cycles) is obtained. Moreover, emission performances of micro‐emitter arrays are found to exhibit good uniformity. The outstanding stability, reproducibility, and uniformity of the thermionic electron micro‐emitter arrays imply their promising applications as on‐chip integrated electron sources.     

Design of Monolithic Tunable CMOS Band-Pass Filter Using Current Feedback Operational Amplifiers

We propose in this paper a tunable second order band-pass filter based on two CMOS current feedback operational amplifiers (CFOAs). The CFOA includes a novel offset compensation technique. A digital building block is implemented in the proposed band-pass filter to tune its central frequency. An important feature of the adopted tuning procedure is the ability to tune the filter without affecting other characteristics such as gain, phase and quality factor. The band-pass filter topology is validated with a configuration where the central frequency is tuned from 60 MHz to 95 MHz with frequency steps of 5 MHz. Measurements of the offset-compensated CFOA are promising, and simulation results of the CFOA-based band-pass filter using the 0.18 μ m CMOS process confirm our theoretical analysis.     

An active inductor employing a new four terminal floating nullor transconductance amplifier (FTFNTA)

ABSTRACT

In this scientific study, a new analog active building block named as four terminal floating nullor transconductance amplifier (FTFNTA) is implemented. The FTFNTA design offers a combined essence of both traditional four terminal floating nullor (FTFN) and an operational transconductance amplifier (OTA). The FTFNTA design is extended for the design of a lossless floating and grounded inductor simulator with few passive components. In addition, the performance and usefulness of the proposed inductor topology are also expanded for active filter applications: higher-order Butterworth high-pass filter and current mode multifunction filter. The functionality of the CMOS-based FTFNTA is integrated with a 0.18 µm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology. Moreover, the FTFNTA is also realised using the current feedback operational amplifier (CFOA/AD844) and OTA (OTA/CA3080) of a commercially available IC to test the viability of the proposed inductor design. Finally, an application based on the inductor topology and its impedance characteristics are well analysed via PSPICE simulation.     

MISO current mode bi-quadratic filter employing high performance inverting second generation current conveyor circuit

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths.Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption.The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results.     

A CMOS Frequency Synthesizer Block for MB‐OFDM UWB Systems

A CMOS frequency synthesizer block for multi‐band orthogonal frequency division multiplexing ultra‐wideband systems is proposed. The proposed frequency synthesizer adopts a double‐conversion architecture for simplicity and to mitigate spur suppression requirements for out‐of‐band interferers in 2.4 and 5 GHz bands. Moreover, the frequency synthesizer can consist of the fewest nonlinear components, such as divide‐by‐Ns and a mixer with the proposed frequency plan, leading to the generation of less spurs. To evaluate the feasibility of the proposed idea, the frequency synthesizer block is implemented in 0.18‐µm CMOS technology. The measured sideband suppression ratio is about 32 dBc, and the phase noise is ‐105 dBc/Hz at an offset of 1 MHz. The fabricated chip consumes 17.6 mA from a 1.8 V supply, and the die‐area including pads is 0.9 × 1.1 mm².     

A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

A 10-bit CMOS cyclic D/A converter based on an improved Johnson counter and a capacitor swapping technique is described. In order to reduce the capacitor mismatching errors, we propose that two capacitors are alternately swapped depending on the input data. Further, a half differential architecture to reduce offset errors and an improved Johnson counter are also discussed. With a 0.35 µm Samsung CMOS technology, the measured SFDR is about 65 dB, when the input frequency is 1 MHz at a clock frequency of 2 MHz. The power consumption is only 240 µW at 3.3 V power supply. The measured INL and DNL are within ±0.7 and ±0.7 LSB, respectively.     

Autodiffusion: a novel method for emitter formation in crystalline silicon thin‐film solar cells

The in situ formation of an emitter in monocrystalline silicon thin‐film solar cells by solid‐state diffusion of dopants from the growth substrate during epitaxy is demonstrated. This approach, that we denote autodiffusion, combines the epitaxy and the diffusion into one single process. Layer‐transfer with porous silicon (PSI process) is used to fabricate n‐type silicon thin‐film solar cells. The cells feature a boron emitter on the cell rear side that is formed by autodiffusion. The sheet resistance of this autodiffused emitter is 330 Ω/□. An independently confirmed conversion efficiency of (14·5 ± 0·4)% with a high short circuit current density of (33·3 ± 0·8) mA/cm² is achieved for a 2 × 2 cm² large cell with a thickness of (24 ± 1) µm. Transferred n‐type silicon thin films made from the same run as the cells show effective carrier lifetimes exceeding 13 µs. From these samples a bulk diffusion length L > 111 µm is deduced. Amorphous silicon is used to passivate the rear surface of these samples after the layer‐transfer resulting in a surface recombination velocity lower than 38 cm/s. Copyright © 2006 John Wiley & Sons, Ltd.     

A 3.1 to 5 GHz CMOS Transceiver for DS‐UWB Systems

This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm² die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network.