A Low Power Analog CMOS Vision Chip for Edge Detection Using Electronic Switches

An analog CMOS vision chip for edge detection with power consumption below 20 mW was designed by adopting electronic switches. An electronic switch separates the edge detection circuit into two parts: one is a logarithmic compression photocircuit, and the other is a signal processing circuit for edge detection. The electronic switch controls the connection between the two circuits. When the electronic switch is off, it can intercept the current flow through the signal processing circuit and restrict the magnitude of the current flow below several hundred nA. The estimated power consumption of the chip, with 128 × 128 pixels, was below 20 mW. The vision chip was designed using 0.25 µm 1‐poly 5‐metal standard full custom CMOS process technology.     

Retina‐Motivated CMOS Vision Chip Based on Column Parallel Architecture and Switch‐Selective Resistive Network

A bio‐inspired vision chip for edge detection was fabricated using 0.35 μm double‐poly four‐metal complementary metal‐oxide‐semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of 160×120 pixels has been fabricated in 5×5 mm² silicon die. It shows less than 10 mW of power consumption.     

具有视网膜仿生处理功能的CMOS图像传感器

借鉴生物视网膜进行图像采集和处理的结构及功能,设计了具有视网膜仿生片上信号处理电路的智能CMOS图像传感器(CIS)。像元内的仿生处理电路主要由自适应光接受器、滤波网络和减法运算电路3部分构成;CIS采用结构简单的空间滤波电阻网络和基于运算放大器的减法电路分别模拟水平细胞和双极细胞的功能,实现图像的边缘检测。在Chartered 0.35μm 2P4M CMOS工艺参数下,对各单元电路及6×6 CIS阵列进行仿真。     

Network‐coded multiple‐source cooperation aided relaying for free‐space optical transmission

A network‐coded cooperative relaying aided free‐space optical (FSO) transmission scheme is designed. The resultant multiple‐source cooperation diversity is exploited by the relay to mitigate the strong turbulence‐induced fading experienced in FSO channels. At the destination, an iterative multiple source detection algorithm is proposed in conjunction with a chip‐level soft network decoding method. Our performance evaluation results using simulation analysis demonstrate that the proposed FSO multiple source detection is capable of approaching the single‐user‐bound for transmission over Gamma–Gamma turbulence channels. Also, the network‐coded cooperative FSO scheme can achieve a significant BER improvement in comparison with conventional noncooperation schemes. Copyright © 2012 John Wiley & Sons, Ltd.     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

An S‐Band Multifunction Chip with a Simple Interface for Active Phased Array Base Station Antennas

An S‐band multifunction chip with a simple interface for an active phased array base station antenna for next‐generation mobile communications is designed and fabricated using commercial 0.5‐μm GaAs pHEMT technology. To reduce the cost of the module assembly and to reduce the number of chip interfaces for a compact transmit/receive module, a digital serial‐to‐parallel converter and an active bias circuit are integrated into the designed chip. The chip can be controlled and driven using only five interfaces. With 6‐bit phase shifting and 6‐bit attenuation, it provides a wideband performance employing a shunt‐feedback technique for amplifiers. With a compact size of 16 mm² (4 mm × 4 mm), the proposed chip exhibits a gain of 26 dB, a P1dB of 12 dBm, and a noise figure of 3.5 dB over a wide frequency range of 1.8 GHz to 3.2 GHz.     

An Analog Front‐End Circuit for ISO/IEC 14443‐Compatible RFID Interrogators

An analog front‐end circuit for ISO/IEC 14443‐compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a 0.25 µm double‐poly CMOS process. The fabricated chip was operated using a 3.3 Volt single‐voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single‐chip ISO/IEC 14443‐compatible RFID interrogators.     

Monolithic SiGe Up‐/Down‐Conversion Mixers with Active Baluns

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on‐chip 1 to 6 GHz up‐conversion and 1 to 8 GHz down‐conversion mixers using a 0.8 µm SiGe hetero‐junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up‐conversion mixer was implemented on‐chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up‐conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down‐conversion mixer was implemented on‐chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down‐conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

A D‐Band Balanced Subharmonically‐Pumped Resistive Mixer Based on 100‐nm mHEMT Technology

A D‐band subharmonically‐pumped resistive mixer has been designed, processed, and experimentally tested. The circuit is based on a 180° power divider structure consisting of a Lange coupler followed by a λ/4 transmission line (at local oscillator (LO) frequency). This monolithic microwave integrated circuit (MMIC) has been realized in coplanar waveguide technology by using an InAlAs/InGaAs‐based metamorphic high electron mobility transistor process with 100‐nm gate length. The MMIC achieves a measured conversion loss between 12.5 dB and 16 dB in the radio frequency bandwidth from 120 GHz to 150 GHz with 4‐dBm LO drive and an intermediate frequency of 100 MHz. The input 1‐dB compression point and IIP3 were simulated to be 2 dBm and 13 dBm, respectively.     

Low‐Voltage Current‐Sensing CMOS Interface Circuit for Piezo‐Resistive Pressure Sensor

A new low‐voltage CMOS interface circuit with digital output for piezo‐resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo‐resistance due to applied pressure and to allow low‐voltage circuit operation. A simple 1‐bit first‐order delta‐sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 µm CMOS technology and draws less than 200 µA from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non‐linearity error.     

AlGaN/GaN Based Ultra‐wideband 15‐W High‐Power Amplifier with Improved Return Loss

An ultra‐wideband microwave monolithic integrated circuit high‐power amplifier with excellent input and output return losses for phased array jammer applications was designed and fabricated using commercial 0.25‐μm AlGaN/GaN technology. To improve the wideband performance, resistive matching and a shunt feedback circuit are employed. The input and output return losses were improved through a balanced design using Lange‐couplers. This three‐stage amplifier can achieve an average saturated output power of 15 W, and power added efficiency of 10% to 28%, in a continuous wave operation over a frequency range of 6 GHz to 18 GHz. The input and output return losses were demonstrated to be lower than over a wide frequency range.     

Measuring the edge‐to‐edge available bandwidth in a DiffServ domain

The new Internet will be deployed with a number of tools for network management and quality of service control. To this end, we focus on a single administrative domain based on the Differentiated Services architectural model, and we recognize the need for two main functions for each supported traffic class: an admission control procedure, and a monitoring of the edge‐to‐edge bandwidth availability. In this work, we specifically focus on the second issue. To preserve scalability and thus to be compliant with Differentiated Services architecture, we propose stateless and distributed procedures based on traffic measurements. Our technique tests network resources by means of ‘special’ probing packets, which have the task of implicitly conveying the network status to its edges. We show by means of simulations the effectiveness of our solutions, in spite of a very low overhead. Copyright © 2007 John Wiley & Sons, Ltd.     

5. 8GHz 堆叠式功率放大器设计

基于2mm GaAs HBT 工艺,采用堆叠晶体管结构设计了一款5. 8GHz 功率放大器。通常堆叠式功率 放大器在高频情况下,上下两层晶体管间需要电感来完成功率匹配,在芯片设计中其电感会增加版图面积和级间功 耗,为此该设计则利用上层晶体管的基极与地之间的串联电阻、电容等效成堆叠结构级间的感性负载,从而减小了 级间的损耗与匹配难度。实测结果表明,该堆叠功率放大器在5. 8GHz 时增益为20. 6dB,饱和输出功率为29dBm,饱 和输出时功率附加效率达到36. 4%,芯片面积仅为1×0. 85mm2     

新型阻变存储器内的电压解决方案

相对于现在流行的FLASH型存储器,新型阻变存储器(resistive-RAM,RRAM)有很多优势,比如较高的存储密度和较快的读写速度。而针对RRAM的读写操作特性,提出了一种适用于新型阻变存储器的提供操作电压的电路。该方案解决了新型存储器需要外部提供高于电源电压的操作电压的问题,使得阻变存储器能应用于嵌入式设备。同时,对工艺波动和温度波动进行补偿,从而降低了阻变存储器的读写操作在较差的工艺和温度环境下的失败概率,具有很强的实际应用意义。该设计采用0.13μm标准CMOS 6层金属工艺在中芯国际(SMIC)流片实现,测试结果表明,采用此电路的RRAM能正确地进行数据编程和擦除等操作,测试结果达到设计要求。     

Wideband Low‐Reflection Transmission Lines for Bare Chip on Multilayer PCB

The pad pitch of modern radio frequency integrated circuits is in the order of few tens of micrometers. Connecting a large number of high‐speed I/Os to the outside world with good signal fidelity at low cost is an extremely challenging task. To cope with this requirement, we need reflection‐free transmission lines from an on‐chip pad to on‐board SMA connectors. Such a transmission line is very hard to design due to the difference in on‐chip and on‐board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow‐to‐wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection‐free microstrip. To verify the concept, several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that the impedance variation is less than 3 Ω for a 50 Ω microstrip and S11 better than –9 dB for the frequency range 1 GHz to 6 GHz when the width changes from 165 µm to 940 µm, and substrate thickness changes from 100 µm to 500 µm.     

一种连接器端子测试仪的设计与实现

为了解决连接器次品快速检测的问题,本文设计并实现了一种连接器端子测试仪.本设计是以ST公司的STM32F407芯片为核心,利用连接器各端点之间的分布电容特性,设计出少点检测电路,能快速检测出连接器的短路或少点等缺陷.实测效果表明,该仪器具有检测后效果好、切实可行、经济方便、稳定可靠、易于用户操作等特点,具有较高的经济效益和较好的实用价值,对相关企业实现自动检测连接器故障具有一定的现实意义.     

Three‐stream network with context convolution module for human–object interaction detection

Human–object interaction (HOI) detection is a popular computer vision task that detects interactions between humans and objects. This task can be useful in many applications that require a deeper understanding of semantic scenes. Current HOI detection networks typically consist of a feature extractor followed by detection layers comprising small filters (eg, 1 × 1 or 3 × 3). Although small filters can capture local spatial features with a few parameters, they fail to capture larger context information relevant for recognizing interactions between humans and distant objects owing to their small receptive regions. Hence, we herein propose a three‐stream HOI detection network that employs a context convolution module (CCM) in each stream branch. The CCM can capture larger contexts from input feature maps by adopting combinations of large separable convolution layers and residual‐based convolution layers without increasing the number of parameters by using fewer large separable filters. We evaluate our HOI detection method using two benchmark datasets, V‐COCO and HICO‐DET, and demonstrate its state‐of‐the‐art performance.     

A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

悬臂梁式硅微加速度计的研制

介绍一种悬臂梁式硅微加速度计的结构与工作原理,并利用ANSYS软件进行了仿真模拟。采用体硅“无掩膜”腐蚀技术,对设计出的敏感芯片进行了工艺试制。通过合理的设计,使挠性梁腐蚀区域侧面上产生(311)面,通过控制所产生的(311)面对(111)面的侵削作用,获得了所需结构。为提高灵敏度和线性,该加速度计采用静电力反馈闭环控制方式,检测与处理电路采用高精度双极线性电路工艺进行了工艺流片。利用多芯片组装工艺进行了敏感芯片与一次集成的检测和处理电路的混合封装。经测试硅微加速度计性能为量程±50g,分辨率3×10–3g,非线性<5×10–4,质量为9.6g。