Cover Picture: Bilayer Organic–Inorganic Gate Dielectrics for High‐Performance,Low‐Voltage,Single‐Walled Carbon Nanotube Thin‐Film Transistors,Complementary Logic Gates,and p–n Diodes on Plastic Substrates (Adv. Funct. Mater. 18/2006)

Low‐voltage, hysteresis‐free, flexible thin‐film‐type electronic systems based on networks of single‐walled carbon nanotubes and bilayer organic–inorganic nanodielectrics are detailed in work by Rogers and co‐workers reported on p. 2355. The cover image shows a schematic array of such thin‐film transistors (TFTs) on a plastic substrate. The structure of the bilayer nanodielectric, which consists of a film of HfO₂ formed by atomic layer deposition and an ultrathin layer of epoxy formed by spin‐casting, is also illustrated schematically. High‐capacitance bilayer dielectrics based on atomic‐layer‐deposited HfO₂ and spin‐cast epoxy are used with networks of single‐walled carbon nanotubes (SWNTs) to enable low‐voltage, hysteresis‐free, and high‐performance thin‐film transistors (TFTs) on silicon and flexible plastic substrates. These HfO₂–epoxy dielectrics exhibit excellent properties including mechanical flexibility, large capacitance (up to ca. 330 nF cm^–2), and low leakage current (ca. 10^–8 A cm^–2); their low‐temperature (ca. 150 °C) deposition makes them compatible with a range of plastic substrates. Analysis and measurements of these dielectrics as gate insulators in SWNT TFTs illustrate several attractive characteristics for this application. Their compatibility with polymers used for charge‐transfer doping of SWNTs is also demonstrated through the fabrication of n‐channel SWNT TFTs, low‐voltage p–n diodes, and complementary logic gates.     

Synthesis and Properties of a Water‐Soluble Single‐Walled Carbon Nanotube–Poly(m‐aminobenzene sulfonic acid) Graft Copolymer

Poly(m‐aminobenzene sulfonic acid) (PABS), was covalently bonded to single‐walled carbon nanotubes (SWNTs) to form a water‐soluble nanotube–polymer compound (SWNT–PABS). The conductivity of the SWNT–PABS graft copolymer was about 5.6 × 10^–3 S cm^–1, which is much higher than that of neat PABS (5.4 × 10^–7 S cm^–1). The mid‐IR spectrum confirmed the formation of an amide bond between the SWNTs and PABS. The ¹H NMR spectrum of SWNT–PABS showed the absence of free PABS, while the UV/VIS/NIR spectrum of SWNT–PABS showed the presence of the interband transitions of the semiconducting SWNTs and an absorption at 17 750 cm^–1 due to the PABS addend.     

Water‐Induced Scandium Oxide Dielectric for Low‐Operating Voltage n‐ and p‐Type Metal‐Oxide Thin‐Film Transistors

Solution‐processed metal‐oxide thin films based on high dielectric constant (k) materials have been extensively studied for use in low‐cost and high‐performance thin‐film transistors (TFTs). Here, scandium oxide (ScO_x) is fabricated as a TFT dielectric with excellent electrical properties using a novel water‐inducement method. The thin films are annealed at various temperatures and characterized by using X‐ray diffraction, atomic‐force microscopy, X‐ray photoelectron spectroscopy, optical spectroscopy, and a series of electrical measurements. The optimized ScO_x thin film exhibits a low‐leakage current density of 0.2 nA cm^?2 at 2 MV cm^?1, a large areal capacitance of 460 nF cm^?2 at 20 Hz and a permittivity of 12.1. To verify the possible applications of ScO_x thin films as the gate dielectric in complementary metal oxide semiconductor (CMOS) electronics, they were integrated in both n‐type InZnO (IZO) and p‐type CuO TFTs for testing. The water‐induced full oxide IZO/ScO_x TFTs exhibit an excellent performance, including a high electron mobility of 27.7 cm² V^?1 s^?1, a large current ratio (I_on/I_off) of 2.7 × 10⁷ and high stability. Moreover, as far as we know it is the first time that solution‐processed p‐type oxide TFTs based on a high‐k dielectric are achieved. The as‐fabricated p‐type CuO/ScO_x TFTs exhibit a large I_on/I_off of around 10⁵ and a hole mobility of 0.8 cm² V^?1 at an operating voltage of 3 V. To the best of our knowledge, these electrical parameters are among the highest performances for solution‐processed p‐type TFTs, which represents a great step towards the achievement of low‐cost, all‐oxide, and low‐power consumption CMOS logics.     

High‐Mobility ZnO Thin Film Transistors Based on Solution‐processed Hafnium Oxide Gate Dielectrics

The properties of metal oxides with high dielectric constant (k) are being extensively studied for use as gate dielectric alternatives to silicon dioxide (SiO₂). Despite their attractive properties, these high‐k dielectrics are usually manufactured using costly vacuum‐based techniques. In that respect, recent research has been focused on the development of alternative deposition methods based on solution‐processable metal oxides. Here, the application of the spray pyrolysis (SP) technique for processing high‐quality hafnium oxide (HfO₂) gate dielectrics and their implementation in thin film transistors employing spray‐coated zinc oxide (ZnO) semiconducting channels are reported. The films are studied by means of admittance spectroscopy, atomic force microscopy, X‐ray diffraction, UV–Visible absorption spectroscopy, FTIR, spectroscopic ellipsometry, and field‐effect measurements. Analyses reveal polycrystalline HfO₂ layers of monoclinic structure that exhibit wide band gap (≈5.7 eV), low roughness (≈0.8 nm), high dielectric constant (k ≈ 18.8), and high breakdown voltage (≈2.7 MV/cm). Thin film transistors based on HfO₂/ZnO stacks exhibit excellent electron transport characteristics with low operating voltages (≈6 V), high on/off current modulation ratio (～10⁷) and electron mobility in excess of 40 cm² V^?1 s^?1.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

Highly Stretchable,High‐Mobility,Free‐Standing All‐Organic Transistors Modulated by Solid‐State Elastomer Electrolytes

Highly stretchable, high‐mobility, and free‐standing coplanar‐type all‐organic transistors based on deformable solid‐state elastomer electrolytes are demonstrated using ionic thermoplastic polyurethane (i‐TPU), thereby showing high reliability under mechanical stimuli as well as low‐voltage operation. Unlike conventional ionic dielectrics, the i‐TPU electrolyte prepared herein has remarkable characteristics, i.e., a large specific capacitance of 5.5 µF cm^?2, despite the low weight ratio (20 wt%) of the ionic liquid, high transparency, and even stretchability. These i‐TPU‐based organic transistors exhibit a mobility as high as 7.9 cm² V^?1 s^?1, high bendability (R_c, radius of curvature: 7.2 mm), and good stretchability (60% tensile strain). Moreover, they are suitable for low‐voltage operation (V_DS = ?1.0 V, V_GS = ?2.5 V). In addition, the electrical characteristics such as mobility, on‐current, and threshold voltage are maintained even in the concave and convex bending state (bending tensile strain of ≈3.4%), respectively. Finally, free‐standing, fully stretchable, and semi‐transparent coplanar‐type all‐organic transistors can be fabricated by introducing a poly(3,4‐ethylenedioxythiophene):polystyrene sulfonic acid layer as source/drain and gate electrodes, thus achieving low‐voltage operation (V_DS = ?1.5 V, V_GS = ?2.5 V) and an even higher mobility of up to 17.8 cm² V^?1 s^?1. Moreover, these devices withstand stretching up to 80% tensile strain.     

Implementation of Low‐Power Electronic Devices Using Solution‐Processed Tantalum Pentoxide Dielectric

The development of solution‐processed field effect transistors (FETs) based on organic and hybrid materials over the past two decades has demonstrated the incredible potential in these technologies. However, solution processed FETs generally require impracticably high voltages to switch on and off, which precludes their application in low‐power devices and prevent their integration with standard logic circuitry. Here, a universal and environmentally benign solution‐processing method for the preparation of Ta₂O₅, HfO₂ and ZrO₂ amorphous dielectric thin films is demonstrated. High mobility CdS FETs are fabricated on such high‐κ dielectric substrates entirely via solution‐processing. The highest mobility, 2.97 cm² V^?1 s^?1 is achieved in the device with Ta₂O₅ dielectric with a low threshold voltage of 1.00 V, which is higher than the mobility of the reference CdS FET with SiO₂ dielectric with an order of magnitude decrease in threshold voltage as well. Because these FETs can be operated at less than 5 V, they may potentially be integrated with existing logic and display circuitry without significant signal amplification. This report demonstrates high‐mobility FETs using solution‐processed Ta₂O₅ dielectrics with drastically reduced power consumption; ≈95% reduction compared to that of the device with a conventional SiO₂ gate dielectric.     

Transparent Photo‐Stable Complementary Inverter with an Organic/Inorganic Nanohybrid Dielectric Layer

Transparent electronics has been one of the key terminologies forecasting the ubiquitous technology era. Several researchers have thus extensively developed transparent oxide‐based thin‐film transistors (TFTs) on glass and plastic substrates. However, work in transparent electronics has been limited mostly to high‐voltage devices operating at more than a few tens of volts, and has mainly focused on transparent display drivers. Low‐voltage logic devices, such as transparent complementary inverters, operating in an electrically stable and photo‐stable manner, are now very necessary to practically realize transparent electronics. Electrically stable dielectrics with high strength and high capacitance must also be proposed to support this mission, and simultaneously these dielectrics must be compatible with both n‐ and p‐channel TFTs in device fabrication. Here, a nanohybrid dielectric layer that is composed of multiple units of inorganic oxide and organic self‐assembled monolayer is proposel to support a transparent complementary TFT inverter operating at 3 V.     

Core‐Brominated Tetraazaperopyrenes as n‐Channel Semiconductors for Organic Complementary Circuits on Flexible Substrates

Organic thin‐film transistors (TFTs) are prepared by vacuum deposition and solution shearing of 2,9‐bis(perfluoroalkyl)‐substituted tetraazaperopyrenes (TAPPs) with bromine substituents at the aromatic core. The TAPP derivatives are synthesized by reacting known unsubstituted TAPPs with bromine in fuming sulphuric acid, and their electrochemical properties are studied in detail by cyclic voltammetry and modelled with density functional theory (DFT) methods. Lowest unoccupied molecular orbital (LUMO) energies and electron affinities indicate that the core‐brominated TAPPs should exhibit n‐channel semiconducting properties. Current‐voltage characteristics of the TFTs established electron mobilities of up to μ_n = 0.032 cm² V^?1 s^?1 for a derivative which was subsequently processed in the fabrication of a complementary ring oscillator on a flexible plastic substrate (PEN).     

Low‐Temperature,Nontoxic Water‐Induced Metal‐Oxide Thin Films and Their Application in Thin‐Film Transistors

Here, a simple, nontoxic, and inexpensive “water‐inducement” technique for the fabrication of oxide thin films at low annealing temperatures is reported. For water‐induced (WI) precursor solution, the solvent is composed of water without additional organic additives and catalysts. The thermogravimetric analysis indicates that the annealing temperature can be lowered by prolonging the annealing time. A systematic study is carried out to reveal the annealing condition dependence on the performance of the thin‐film transistors (TFTs). The WI indium‐zinc oxide (IZO) TFT integrated on SiO₂ dielectric, annealed at 300 °C for 2 h, exhibits a saturation mobility of 3.35 cm² V^?1 s^?1 and an on‐to‐off current ratio of ≈10⁸. Interestingly, through prolonging the annealing time to 4 h, the electrical parameters of IZO TFTs annealed at 230 °C are comparable with the TFTs annealed at 300 °C. Finally, fully WI IZO TFT based on YO_x dielectric is integrated and investigated. This TFT device can be regarded as “green electronics” in a true sense, because no organic‐related additives are used during the whole device fabrication process. The as‐fabricated IZO/YO_x TFT exhibits excellent electron transport characteristics with low operating voltage (≈1.5 V), small subthreshold swing voltage of 65 mV dec^?1 and the mobility in excess of 25 cm² V^?1 s^?1.     

Polymer Light‐Emitting Electrochemical Cells: Doping Concentration,Emission‐Zone Position,and Turn‐On Time

Direct optical probing of the doping progression and simultaneous recording of the current–time behavior allows the establishment of the position of the light‐emitting p–n junction, the doping concentrations in the p‐ and n‐type regions, and the turn‐on time for a number of planar light‐emitting electrochemical cells (LECs) with a 1 mm interelectrode gap. The position of the p–n junction in such LECs with Au electrodes contacting an active material mixture of poly(2‐methoxy‐5‐(2′‐ethylhexyloxy)‐p‐phenylene vinylene) (MEH‐PPV), poly(ethylene oxide), and a XCF₃SO₃ salt (X = Li, K, Rb) is dependent on the salt selection: for X = Li the p–n junction is positioned very close to the negative electrode, while for X = K, Rb it is significantly more centered in the interelectrode gap. Its is demonstrated that this results from that the p‐type doping concentration is independent of salt selection at ca. 2 × 10²⁰ cm^–3 (ca. 0.1 dopants/MEH‐PPV repeat unit), while the n‐type doping concentration exhibits a strong dependence: for X = K it is ca. 5 × 10²⁰ cm^–3 (ca. 0.2 dopants/repeat unit), for X = Rb it is ca. 9 × 10²⁰ cm^–3 (ca. 0.4 dopants/repeat unit), and for X = Li it is ca. 3 × 10²¹ cm^–3 (ca. 1 dopants/repeat unit). Finally, it is shown that X = K, Rb devices exhibit significantly faster turn‐on times than X = Li devices, which is a consequence of a higher ionic conductivity in the former devices.     

Capacitively Coupled Hybrid Ion Gel and Carbon Nanotube Thin‐Film Transistors for Low Voltage Flexible Logic Circuits

The lamination of a high‐capacitance ion gel dielectric layer onto semiconducting carbon nanotube (CNT) thin‐film transistors (TFTs) that are bottom‐gated with a low‐capacitance polymer dielectric layer drastically reduces the operating voltage of the devices resulting from the capacitive coupling effect between the two dielectric layers sandwiching the CNT channel. As the CNT channel has a network structure, only a compact area of ion gel is required to make the capacitive coupling effect viable, unlike the planar channels of previously reported transistors that required a substantially larger area of ion gel dielectric layer to induce the coupling effect. The capacitively coupled CNT TFTs possess superlative electrical characteristics such as high carrier mobilities (42.0 cm² (Vs)^?1 for holes and 59.1 cm² (Vs)^?1 for electrons), steep subthreshold swings (160 mV dec^?1 for holes and 100 mV dec^?1 for electrons), and low gate leakage currents (<1 nA). These devices can be further integrated to form complex logic circuits on flexible substrates with high mechanical resilience. The layered geometry of the device coupled with scalable solution‐based fabrication has significant potential for large‐scale flexible electronics.     

High‐Performance,Air‐Stable,Top‐Gate,p‐Channel WSe2 Field‐Effect Transistor with Fluoropolymer Buffer Layer

High‐performance, air‐stable, p‐channel WSe₂ top‐gate field‐effect transistors (FETs) using a bilayer gate dielectric composed of high‐ and low‐k dielectrics are reported. Using only a high‐k Al₂O₃ as the top‐gate dielectric generally degrades the electrical properties of p‐channel WSe₂, therefore, a thin fluoropolymer (Cytop) as a buffer layer to protect the 2D channel from high‐k oxide forming is deposited. As a result, a top‐gate‐patterned 2D WSe₂ FET is realized. The top‐gate p‐channel WSe₂ FET demonstrates a high hole mobility of 100 cm²_­ V^?1 s^?1 and a I_ON/I_OFF ratio > 10⁷ at low gate voltages (V_GS ca. ?4 V) and a drain voltage (V_DS) of ?1 V on a glass substrate. Furthermore, the top‐gate FET shows a very good stability in ambient air with a relative humidity of 45% for 7 days after device fabrication. Our approach of creating a high‐k oxide/low‐k organic bilayer dielectric is advantageous over single‐layer high‐k dielectrics for top‐gate p‐channel WSe₂ FETs, which will lead the way toward future electronic nanodevices and their integration.     

Simultaneous Modification of Bottom‐Contact Electrode and Dielectric Surfaces for Organic Thin‐Film Transistors Through Single‐Component Spin‐Cast Monolayers

An efficient process is developed by spin‐coating a single‐component, self‐assembled monolayer (SAM) to simultaneously modify the bottom‐contact electrode and dielectric surfaces of organic thin‐film transistors (OTFTs). This effi cient interface modifi cation is achieved using n‐alkyl phosphonic acid based SAMs to prime silver bottom‐contacts and hafnium oxide (HfO₂) dielectrics in low‐voltage OTFTs. Surface characterization using near edge X‐ray absorption fi ne structure (NEXAFS) spectroscopy, X‐ray photoelectron spectroscopy (XPS), attenuated total reflectance Fourier transform infrared (ATR‐FTIR) spectroscopy, atomic force microscopy (AFM), and spectroscopic ellipsometry suggest this process yields structurally well‐defi ned phosphonate SAMs on both metal and oxide surfaces. Rational selection of the alkyl length of the SAM leads to greatly enhanced performance for both n‐channel (C₆₀) and p‐channel (pentacene) based OTFTs. Specifi cally, SAMs of n‐octylphos‐phonic acid (OPA) provide both low‐contact resistance at the bottom‐contact electrodes and excellent interfacial properties for compact semiconductor grain growth with high carrier mobilities. OTFTs based on OPA modifi ed silver electrode/HfO₂ dielectric bottom‐contact structures can be operated using < 3V with low contact resistance (down to 700 Ohm‐cm), low subthreshold swing (as low as 75 mV dec^?1), high on/off current ratios of 107, and charge carrier mobilities as high as 4.6 and 0.8 cm² V^?1 s^?1, for C60 and pentacene, respectively. These results demonstrate that this is a simple and efficient process for improving the performance of bottom‐contact OTFTs.     

Covalently Tethered Polyoxometalate–Pyrene Hybrids for Noncovalent Sidewall Functionalization of Single‐Walled Carbon Nanotubes as High‐Performance Anode Material

A covalently tethered polyoxometalate (POM)–pyrene hybrid (Py–SiW₁₁) is utilized for the noncovalent functionalization of single‐walled carbon nanotubes (SWNTs). The resulting SWNTs/Py–SiW₁₁ nanocomposite shows that both SiW₁₁ and pyrene moieties could interact with SWNTs without causing any chemical decomposition. When used as anode material in lithium‐ion batteries, the SWNTs/Py–SiW₁₁ nanocomposite exhibits higher discharge capacities, and better rate capacity and cycling stability than the individual components. When the current density is 0.5 mA cm^?2, the nanocomposite exhibits the initial discharge capacity of 1569.8 mAh g^?1, and a high discharge capacity of 580 mAh g^?1 for up to 100 cycles.     

Organic Thin‐Film Transistors: Simultaneous Modification of Bottom‐Contact Electrode and Dielectric Surfaces for Organic Thin‐Film Transistors Through Single‐Component Spin‐Cast Monolayers (Adv. Funct. Mater. 8/2011)

An efficient process is developed by spin‐coating a single‐component, self‐assembled monolayer (SAM) to simultaneously modify the bottom‐contact electrode and dielectric surfaces of organic thin‐film transistors (OTFTs). This effi cient interface modifi cation is achieved using n‐alkyl phosphonic acid based SAMs to prime silver bottom‐contacts and hafnium oxide (HfO₂) dielectrics in low‐voltage OTFTs. Surface characterization using near edge X‐ray absorption fi ne structure (NEXAFS) spectroscopy, X‐ray photoelectron spectroscopy (XPS), attenuated total reflectance Fourier transform infrared (ATR‐FTIR) spectroscopy, atomic force microscopy (AFM), and spectroscopic ellipsometry suggest this process yields structurally well‐defi ned phosphonate SAMs on both metal and oxide surfaces. Rational selection of the alkyl length of the SAM leads to greatly enhanced performance for both n‐channel (C₆₀) and p‐channel (pentacene) based OTFTs. Specifi cally, SAMs of n‐octylphos‐phonic acid (OPA) provide both low‐contact resistance at the bottom‐contact electrodes and excellent interfacial properties for compact semiconductor grain growth with high carrier mobilities. OTFTs based on OPA modifi ed silver electrode/HfO₂ dielectric bottom‐contact structures can be operated using < 3V with low contact resistance (down to 700 Ohm‐cm), low subthreshold swing (as low as 75 mV dec^?1), high on/off current ratios of 107, and charge carrier mobilities as high as 4.6 and 0.8 cm² V^?1 s^?1, for C60 and pentacene, respectively. These results demonstrate that this is a simple and efficient process for improving the performance of bottom‐contact OTFTs.     

Enhanced Performance of Self‐Assembled Monolayer Field‐Effect Transistors with Top‐Contact Geometry through Molecular Tailoring,Heated Assembly,and Thermal Annealing

Low‐voltage self‐assembled monolayer field‐effect transistors (SAMFETs) that operate under an applied bias of less than ?3 V and a high hole mobility of 10^?2 cm² V^?1 s^?1 are reported. A self‐assembled monolayer (SAM) with a quaterthiophene semiconducting core and a phosphonic acid binding group is used to fabricate SAMFETs on both high‐voltage (AlO_x/300 nm SiO₂) and low‐voltage (HfO₂) dielectric platforms. High performance is achieved through enhanced SAM packing density via a heated assembly process and through improved electrical contact between SAM semiconductor and metal electrodes. Enhanced electrical contact is obtained by utilizing a functional methylthio head group combined with thermal annealing post gold source/drain electrode deposition to facilitate the interaction between SAM and electrode.     

A 4 V Operation,Flexible Braille Display Using Organic Transistors,Carbon Nanotube Actuators,and Organic Static Random‐Access Memory

A sheet‐type Braille display operating at 4 V has been successfully fabricated by integrating organic an static random‐access memory (SRAM) array with carbon nanotube (CNT)‐based actuators that are driven by organic thin‐film transistors (control‐TFTs). The on current of organic control‐TFTs that drive CNT actuators exceeds 3 mA, the mobility exceeds 1 cm² V^?1s^?1, and the on/off ratio exceeds 10⁵ at an operational voltage of 3 V. By adjusting the process time for the formation of the aluminum oxide dielectrics, the threshold voltage of the organic TFTs can be systematically controlled. This technique leads to an improved static noise margin of the SRAM and enables its stable operation with a short programming time of 2 ms at a programming voltage of 2 V. As a demonstration of the operation of one actuator with one control‐TFT and SRAM: the displacement of actuator exceeds 300 μm at an operation voltage of 4 V, which is large enough for a blind person to recognize the pop‐up of braille dots. Integrating the SRAM array reduces the frame rate of a 12 dot × 12 dot display from 1/21.6 s to 1/2.9 s.     

Polyazines and Polyazomethines with Didodecylthiophene Units for Selective Dispersion of Semiconducting Single‐Walled Carbon Nanotubes

Polymer wrapped single‐walled carbon nanotubes (SWNTs) have been demonstrated to be a very efficient technique to obtain high purity semiconducting SWNT solutions. However, the extraction yield of this technique is low compared to other techniques. Poly‐alkyl‐thiophenes have been reported to show higher extraction yield compare to polyfluorene derivatives. Here, the affinity for semiconducting SWNTs of two polymers with a backbone containing didodecylthiophene units interspersed with N atoms is reported. It is demonstrated that one of the polymers, namely, poly(2,5‐dimethylidynenitrilo‐3,4‐didodecylthienylene) (PAMDD), has very high semiconducting SWNT extraction yield compared to the poly(3,4‐didodecylthienylene)azine (PAZDD). The dissimilar wrapping efficiency of these two polymers for semiconducting SWNTs is attributed to the interplay between the affinity for the nitrogen atoms of the highly polarizable walls of SWNTs and the mechanical flexibility of the polymer backbones. Photoluminescence (PL) measurements demonstrate the presence of metallic tubes and SWNT bundles in the sample selected with PAZDD and higher purity of SWNT‐PAMDD samples. The high purity of the semiconducting SWNTs selected by PAMDD is further demonstrated by the high performance of the solution‐processed field‐effect transistors (FETs) fabricated using a blade coating technique, which exhibit hole mobilities up to 33.3 cm² V^?1 s^?1 with on/off ratios of 10⁶.     

A High‐k Fluorinated P(VDF‐TrFE)‐g‐PMMA Gate Dielectric for High‐Performance Flexible Field‐Effect Transistors

A newly synthesized high‐k polymeric insulator for use as gate dielectric layer for organic field‐effect transistors (OFETs) obtained by grafting poly(methyl methacrylate) (PMMA) in poly(vinylidene fluoride‐trifluoroethylene) (P(VDF‐TrFE)) via atom transfer radical polymerization transfer is reported. This material design concept intents to tune the electrical properties of the gate insulating layer (capacitance, leakage current, breakdown voltage, and operational stability) of the high‐k fluorinated polymer dielectric without a large increase in operating voltage by incorporating an amorphous PMMA as an insulator. By controlling the grafted PMMA percentage, an optimized P(VDF‐TrFE)‐g‐PMMA with 7 mol% grafted PMMA showing reasonably high capacitance (23–30 nF cm^?2) with low voltage operation and negligible current hysteresis is achieved. High‐performance low‐voltage‐operated top‐gate/bottom‐contact OFETs with widely used high mobility polymer semiconductors, poly[[2,5‐bis(2‐octyldodecyl)‐2,3,5,6‐tetrahydro‐3,6‐dioxopyrrolo [3,4‐c]pyrrole‐1,4‐diyl]‐alt‐[[2,2′‐(2,5‐thiophene)bis‐thieno(3,2‐b)thiophene]‐5,5′‐diyl]] (DPPT‐TT), and poly([N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)) are demonstrated here. DPPT‐TT OFETs with P(VDF‐TrFE)‐g‐PMMA gate dielectrics exhibit a reasonably high field‐effect mobility of over 1 cm² V^?1 s^?1 with excellent operational stability.