Pendeo-epitaxial growth of gallium nitride on silicon substrates

Pendeo-epitaxy (PE)¹ from raised, [0001] oriented GaN stripes covered with silicon nitride masks has been employed for the growth of coalesced films of GaN(0001) with markedly reduced densities of line and planar defects on Si(111)-based substrates. Each substrate contained previously deposited 3C-SiC(111) and AlN(0001) transition layers and a GaN seed layer from which the stripes were etched. The 3C-SiC transition layer eliminated chemical reactions between the Si and the NH₃ and the Ga metal from the decomposition of triethylgallium. The 3C-SiC and the GaN seed layers, each 0.5 μm thick, were also used to minimize the cracking and warping of the GaN/SiC/silicon assembly caused primarily by the stresses generated on cooling due to the mismatches in the coefficients of thermal expansion. Tilting in the coalesced GaN epilayers of 0.2° was confined to areas of lateral overgrowth over the masks; no tilting was observed in the material suspended above the trenches. The strong, low-temperature PL band-edge peak at 3.456 eV with a FWHM of 17 meV was comparable to that observed in PE GaN films grown on AlN/6H-SiC(0001) substrates.     

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET’s ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor （p-MOSFET） is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si （LT-Si）/10nm S i buffer was grown by Molecular Beam Epitaxy （MBE）, in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET＇s （L=4.2μm） transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm^2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.     

Dissipation loss of mid-infrared radiation in a dielectric waveguide

Dissipation loss of electromagnetic radiation with wavelengths of 20–55 μm was theoretically studied in a three-layer planar dielectric insulating waveguide combined with a heterolaser. It was shown that the dependence of the loss on the waveguide layer thickness behaves differently for different wavelengths in the range of 20–55 μm. The lowest loss (several inverse centimeters) is characteristic of radiation with wavelength λ = 20 μm. The losses increase with the wavelength and reach a value of 150 cm^-1 at λ = 40 μm, which is almost independent of the waveguide layer thickness. For electromagnetic radiation with λ = 50 and 55 μm, a sharp (hundreds of times) decrease in the loss with an increase in the waveguide layer thickness is observed.     

Photoluminescence studies of heteroepitaxial gaas on si

We present a systematic study of the photoluminescence of undoped GaAs layers deposited by MOCVD on Si substrates. The study includes an examination of substrate and layer thickness effects in thin GaAs layers, and a detailed investigation of the stress effects on the intrinsic band-edge transitions in thicker samples. For sample thickness,t ≤ 0.5(μm), we observe strong midgap emission bands associated with defects close to the interface. These bands depend strongly on the nature of the Si substrate. The crystal quality improves with sample thickness, and fort ≥ 0.5 μm the emission is dominated by lines in the band edge region which are relatively independent of substrate preparation. Photoluminescence excitation spectra reveal that the highest energy line is due to an intrinsic exciton transition, and that a splitting of this line observed fort ≥ 2 μm reflects the presence of two different regions of strain in the material. The magnitude of the strain is estimated from the shift of the exciton lines relative to unstrained GaAs, and is found to be consistent with an upper limit provided by the thermal expansion mismatch between GaAs and Si.     

Characterization of polycrystalline 3C-SiC thin film diodes for extreme environment applications

This paper describes the fabrication and characteristics of polycrystalline (poly) 3C-SiC thin film diodes for extreme environment applications, in which the poly 3C-SiC thin film was deposited onto oxidized Si wafers by APCVD using HMDS as a precursor. In this work, the optimized growth temperature and HMDS flow rate were 1100 °C and 8 sccm, respectively. A Schottky diode with a Au, Al/poly 3C-SiC/SiO₂/Si(n-type) structure was fabricated and its threshold voltage (V_d), breakdown voltage, thickness of depletion layer, and doping concentration (N_D) values were measured as 0.84 V, over 140 V, 61 nm, and 2.7 × 10¹⁹ cm³, respectively. To produce good ohmic contact, Al/3C-SiC were annealed at 300, 400, and 500 °C for 30 min under a vacuum of 5.0 × 10⁻⁶ Torr. The obtained p-n junction diode fabricated by poly 3C-SiC had similar characteristics to a single 3C-SiC p-n junction diode.     

The influence of dielectric layers on the CW-Laser Annealing of polysilicon

Polysilicon films were deposited on the following four dielectric layers: 0.10 μm Si0₂, 0.10 μm Si₃N₄, 1.0 μm Si0₂ and a dual layer of 0.10 μm Si₃N₄ over 1.0 μm Si0₂. The films were doped with As or P and then annealed with a scanning CW-argon laser. The resulting sheet resistance at a given laser power depends upon both the dielectric material and its thickness. The threshold power, that causes complete melting of the polysilicon, is inversely proportional to the thermal resistance of the underlying dielectric layers. With certain laser parameters and substrate film combinations, excessive thermal stresses cause cracking of the polysilicon films. The laser annealing process is also influenced by the net optical reflectance of the polysilicon/ dielectric multilayer films.     

X-ray Diffraction Imaging of Improved Bulk-Grown CdZnTe(211) and Its Comparison with Epitaxially Grown CdTe Buffer Layers on Si and Ge Substrates

Large-area high-quality Hg_1–x Cd _x Te sensing layers for infrared imaging in the 8 μm to 12 μm spectral region are typically grown on bulk Cd_1–x Zn _x Te substrates. Alternatively, epitaxial CdTe grown on Si or Ge has been used as a buffer layer for high-quality epitaxial HgCdTe growth. In this paper, x-ray topographs and rocking-curve full-width at half-maximum (FWHM) data will be presented for recent high-quality bulk CdZnTe grown by the vertical gradient freeze (VGF) method, previous bulk CdZnTe grown by the vertical Bridgman technique, epitaxial CdTe buffer layers on Si and Ge, and a HgCdTe layer epitaxially grown on bulk VGF CdZnTe.     

The properties of Si/Si1-xGex films grown on Si substrates by chemical vapor deposition

A growth parameter study was made to determine the proper of a SiGe superlattice-type configuration grown on Si substrates by chemical vapor deposition (CVD). The study included such variables as growth temperature, layer composition, layer thickness, total film thickness, doping concentrations, and film orientation. Si and SiGe layers were grown using SiH₄ as the Si source and GeH₄ as the Ge source. When intentional doping was desired, diluted diborane for p-type films and phosphine for n-type films were used. The study led to films grown at ∼1000°C with mobilities from ∼20 to 40 percent higher than that of epitaxial Si layers and ∼100 percent higher than that of epitaxial SiGe layers grown on (100) Si in the same deposition system for net carrier concentrations of ∼8x10¹⁵ cm^-3 to ∼2x10¹⁷ cm^-3. Enhanced mobilities were found in multilayer (100)-oriented Si/Si_1-xGe_x films for layer thicknesses ≥400A, for film thicknesses >2μm, and for layers with x = 0.15. No enhanced mobility was found for (111)-oriented films and for B-doped multilayered (100)-orlented films. Supported in part by NASA-Langley Research Center, Hampton, VA, Contract NAS1-16102 (R. Stermer & A. Fripp, Contr. Mon.)     

Surface acoustic wave characteristics of ZnO films grown on a polycrystalline 3C-SiC buffer layer

Zinc oxide (ZnO) thin films were deposited onto a polycrystalline (poly) 3C-SiC buffer layer for surface acoustic wave (SAW) applications using a magnetron sputtering system. Atomic force microscopy (AFM) and X-ray diffraction (XRD) showed that the ZnO grown on 3C-SiC/Si had a smooth surface, a dominant c-axis orientation and a lower residual stress in ZnO thin film compared to that grown directly onto Si substrate. In order to evaluate the SAW characteristics of ZnO films on a 3C-SiC buffer layer, the two-port SAW resonators, based on inter-digital transducer (IDT)/ZnO/3C-SiC/Si and IDT/ZnO/Si structures, were fabricated and measured within a temperature range of 25-135 °C. The resulting 3C-SiC buffer layer improved the insertion loss by approximately 7.3 dB within the SAW resonator and enhanced the temperature stability with TCF = −22 ppm/°C up to 135 °C in comparison to that of TCF = −45 ppm/°C within a temperature range of 25-115 °C of the ZnO/Si structure.     

Maskless selective area growth of InP on Sub-μm V-groove patterned Si(001)

Low pressure metalorganic chemical vapor deposition of InP onexactly oriented Si(OOl) substrates with a periodic V-groove pattern of periodicity ≤1.2 μm using a two temperature growth sequence (400 and 640°C) is reported. Planar InP layers with extremely low defect density of 7 × 10⁴ cm⁻² are obtained. For InP on V-grooves of width g ≤1.0μm, a planar surface is formed after less than 1 μm of growth. Formation or suppression of antiphase domains (APDs) is a function of the widths of the (OOl)-oriented ridges. For s ≤1 μm, epilayers are single domain and the direction is oriented parallel to the grooves. At 400°C, nucleation starts homogeneously on {111}-sidewallsand (001)-facets. While heating up to 640°C, InP migrates into the grooves, depleting almost completely the (001)-facets. During growth of the main layer, first the V-grooves are filled up. Subsequently (001)-ridges are overgrown laterally or voids are formed on top of them. This mechanism is responsible for both planarization and APD-suppression. The surface migration length of InP on Si(001) at 640°C is estimated to be ≈0.5 μm.     

Selected-area GaAs epitaxial growth on Si free from detrimental sidewall interactions

The growth of GaAs on patterned Si trenches is essential for the realization of planarized monolithic co-integration of GaAs and Si devices. The patterned boundary regions also provide lateral sinks for stresses and defect propagation so long as the undesirable sidewall growth interactions are suppressed. In this study, we developed a cantilever patterning mask structure, with feature sizes ranging from 1.5 to 100 μm using overhung SiO₂ masks sitting on top of 3-μm-tall undercutting poly-Si patterns. The Si growth surface is protected and unetched. Patterned molecular beam epitaxial (MBE) grown GaAs layers are then prepared with complete elimination of sidewall interactions. Cross-sectional transmission electron microscopy (XTEM) results show there are reduced-defect areas in the regions 2 to 3 μm from the pattern edges compared to blanket grown areas. Combining the near-edge defect-reduction feature with other defect-reduction schemes incorporated during growth, patterned GaAs with sizes of 10 μm or under exhibits significant material quality improvements compared to blanket layer growth under the same conditions.     

Fabrication and Characterization of MOVPE-Grown CdTe-on-Si Heterojunction Diode-Type Gamma-Ray Detectors

We report on the growth of very thick (>260 μm) high-crystalline-quality single-crystal CdTe epitaxial films on (211) Si substrates in a metalorganic vapor-phase epitaxy reactor, and the development of gamma ray detectors and their radiation detection properties. Films were grown with a high growth rate varying from 40 μm/h to 70 μm/h. A heterojunction diode was fabricated by growing a 90-μm-thick CdTe layer on an n ⁺-Si substrate, which exhibited good rectifying behavior and had a low reverse bias leakage current of 0.18 μA/cm² at 100 V bias. The diode clearly demonstrated its gamma radiation detection capability by resolving energy peaks from the ²⁴¹Am radioisotope during room-temperature measurements. By cooling the diode detector to −30°C, the leakage current could be reduced by three orders of magnitude from the room-temperature value. At this operating condition dramatic improvements in the pulse height spectrum were observed.     

Polytype Stability and Microstructural Characterization of Silicon Carbide Epitaxial Films Grown on [ {\hbox{11}}\overline{{\hbox{2}}} {\hbox{0}} ]- and [0001]-Oriented Silicon Carbide Substrates

The polytype and surface and defect microstructure of epitaxial layers grown on 4H(), 4H(0001) on-axis, 4H(0001) 8° off-axis, and 6H(0001) on-axis substrates have been investigated. High-resolution x-ray diffraction (XRD) revealed the epitaxial layers on 4H() and 4H(0001) 8° off-axis to have the 4H-SiC (silicon carbide) polytype, while the 3C-SiC polytype was identified for epitaxial layers on 4H(0001) and 6H(0001) on-axis substrates. Cathodoluminescence (CL), Raman spectroscopy, and transmission electron microscopy (TEM) confirmed these results. The epitaxial surface of 4H() films was specular with a roughness of 0.16-nm root-mean-square (RMS), in contrast to the surfaces of the other epitaxial layer-substrate orientations, which contained curvilinear boundaries, growth pits (∼3 × 10⁴ cm⁻²), triangular defects >100 μm, and significant step bunching. Molten KOH etching revealed large defect densities within 4H() films that decreased with film thickness to ∼10⁶ cm⁻² at 2.5 μm, while cross-sectional TEM studies showed areas free of defects and an indistinguishable film-substrate interface for 4H() epitaxial layers.     

Growth of high quality CdTe and ZnTe on Si substrates using organometallic vapor phase epitaxy

Epitaxial (100) CdTe and ZnTe layers with high crystalline quality have been grown on Si substrates by atmospheric pressure organometallic vapor phase epitaxy (OMVPE). A thin Ge interfacial layer grown at low temperature was used as a buffer layer prior to ZnTe and CdTe growth. The layers were characterized by Nomarski optical microscopy and double crystal x-ray diffraction. Double crystal rocking curves with full width at half maximum of about 110 and 250 arc-sec have been obtained for a 7 μm thick ZnTe layer and a 4 μm thick CdTe layer, respectively. The results presented demonstrate a novel method ofin-situ Si cleaning step without a high temperature deoxidation process to grow high quality CdTe and ZnTe on Si in a single OMVPE reactor.     

Highly Ordered Vertical Silicon Nanowire Array Composite Thin Films for Thermoelectric Devices

The fabrication and characterization of silicon nanowire (NW) array/spin-on glass (SOG) composite films for thermoelectric devices are presented. Interference lithography was used to pattern square lattice photoresist templates over entire 2 cm × 2 cm n-type Si substrates. The photoresist pattern was transferred to a SiO₂ hard mask for a single-step deep reactive ion Si etch. The resulting Si NW arrays were 1 μm tall with 15% packing density, and the individual NWs had diameters of 80 nm to 90 nm with vertical sidewalls. The Si NW arrays were embedded in SOG to form a dense and robust composite material for device fabrication and thin-film characterization. The thermal conductivity of the Si NW/SOG composite film was measured to be a constant 1.45 ± 0.2 W/m-K from 300 K to 450 K. An effective medium model was then used to extract a thermal conductivity of 7.5 ± 1.7 W/m-K for the Si nanowires from the measured Si NW/SOG values. The cross-plane Seebeck coefficient of the Si NWs was measured to be −284 ± 26 μV/K, which is comparable to −310 μV/K for bulk Si. Power generation from the combined Si NW/SOG and substrate devices is also presented, and the maximum generated power was found to be 29.3 μW with ΔT of 56 K for a 50 μm × 50 μm device.     

Fabrication and Characterization of Silicon Microchannel Plates as Temperature-Sensing Materials

Silicon microchannel plates (Si MCPs) are prepared by photo-assisted electrochemical etching (PAECE), and their temperature-sensing behavior based on the Seebeck effect is studied. In particular, the dependence of the temperature sensitivity on the orientation and pore size of the Si MCPs is determined in detail. Our results clarify the relationship between the temperature sensitivity and orientation of the Si MCPs. When the angle between the measured orientation and edge of the square micropore is 45°, the samples with pore dimensions of 5 μm × 5 μm and 3 μm × 3 μm show temperature sensitivities of 1.88 mV/°C and 0.93 mV/°C, respectively. In general, the sample with pore size of 5 μm × 5 μm exhibits higher sensitivity. Si MCPs which are compatible with integrated circuit (IC) processing have promising applications in integrated microtemperature sensing.     

Thermal Stability Study of Cu(MoN<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>) Seed Layer on Barrierless Si

This study reports the good thermal stability of a sputtered Cu(MoN _x ) seed layer on a barrierless Si substrate. A Cu film with a small amount of MoN _x was deposited by reactive co-sputtering of Cu and Mo in an Ar/N₂ gas mixture. After annealing at 560°C for 1 h, no copper silicide formation was observed at the interface of Cu and Si. Leakage current and resistivity evaluations reveal the good thermal reliability of Cu with a dilute amount of MoN _x at temperatures up to 560°C, suggesting its potential application in advanced barrierless metallization. The thermal performance of Cu(MoN _x ) as a seed layer was evaluated when pure Cu is deposited on top. X-ray diffraction, focused ion beam microscopy, and transmission electron microscopy results confirm the presence of an ∼10-nm-thick reaction layer formed at the seed layer/Si interface after annealing at 630°C for 1 h. Although the exact composition and structure of this reaction layer could not be unambiguously identified due to trace amounts of Mo and N, this reaction layer protects Cu from a detrimental reaction with Si. The Cu(MoN _x ) seed layer is thus considered to act as a diffusion buffer with stability up to 630°C for the barrierless Si scheme. An electrical resistivity of 2.5 μΩ cm was obtained for the Cu/Cu(MoN _x ) scheme after annealing at 630°C.     

Optical properties of thin GaSe/<Emphasis Type="Italic">n</Emphasis>-Si(111) films

Morphological and optical studies (ellipsometry and reflectance spectroscopy in the ranges 400–750 nm and 1.4–25 μm) of thin GaSe films fabricated by thermal evaporation on the n-Si (111) single-crystal substrates are reported. The film thickness was 15–60 nm. It is established that, in the initial stage of growth, the growth of GaSe on the n-Si (111) substrates occurs via formation of islands (three-dimensional growth). It is shown that, as the thickness increases, the physical parameters of the film change and the films approach single crystals in crystalline and energy band structure. For films with a thickness of 60 nm, the reflectance band peak is attributed to indirect optical transitions enhanced by reflection from the film-substrate interface. From the results of optical studies, quantum effects in the surface region of the thin films are conjectured.     

Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits

Thermal stress issues in a three-dimensional (3D) stacked wafer system were examined using finite-element analysis of the stacked wafers. This paper elucidates the effects of the bonding dimensions on mechanical failure and the keep-away zone, where devices cannot be located because of the stress in the Si. The key factors in decreasing the thermal strain were the bonding diameter and thickness. When the bonding diameter decreased from 40 μm to 12 μm, the equivalent strain decreased by 83%. It is noteworthy that the keep-away zone also decreased from 17 μm to zero when the bonding diameter decreased from 40 μm to 12 μm. When the bonding thickness doubled, the equivalent strain decreased by 44%. The effects of the dimensions and arrangement of through-silicon vias (TSV) were also analyzed. Small TSV diameter and pitch are important to decrease the equivalent strain, especially when the amount of Cu per unit volume is fixed. When the TSV diameter and pitch decreased fourfold, the equivalent strain decreased by 70%. The effects of TSV height and the number of die stacks were not significant, because the underfill acted as a buffer against thermal strain.     

Si Wafer Thinning Techniques Compatible With Epitaxy of CdTe Buffer Layers

Reduction of threading dislocation density is critical for improving the performance of HgCdTe detectors on lattice-mismatched alternative substrates such as Si. CdTe buffer layers grown by molecular beam epitaxy (MBE), with thicknesses on the order of 8 μm to 12 μm, have helped reduce dislocation densities in HgCdTe layers. In this study, the reduction of threading dislocation densities in CdTe buffer layers grown on locally thinned Si substrates was examined. A novel Si back-thinning technique was developed that maintained an epiready front surface and achieved Si thicknesses as low as 1.9 μm. Threading dislocation densities, acquired by defect decoration techniques, were reduced by as much as 60% for CdTe buffer layers grown on these thinned regions when compared with unthinned regions. However, this reduction is inconsistent with prior notions that threading dislocation propagation is dominated by image forces. Instead, the thickness gradient of thinned Si may play a larger role.