A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM

A mixed-mode delay-locked loop (MDLL) for a 512 Mb graphics SDRAM is presented in this paper. The MDLL extends its lock range into the gigahertz realm by applying clock division and analog phase generation (APG). The divided clock from the MDLL is used for clocking logic and tracking deterministic access latency in the SDRAM. A short discussion of some of the side effects and advantages of using a divided, multi-phase clock for logic operation is presented. A low-power clock distribution network (CDN) based on the presented MDLL is also disclosed. Fabricated in a 1.5 V 95 nm triple-metal CMOS process, the MDLL achieves a measured RMS jitter of 4.6 ps and peak-to-peak jitter of 38 ps at GDDR4 mode with a 1 GHz clock. Power consumption for the entire MDLL-based CDN is 107 mW at 800 MHz and 1.5 V.     

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

In this paper, a delay-locked loop (DLL)-based clock generator is presented. Although a DLL-based clock generator requires a clean reference signal, it has several inherent advantages over conventional phase-locked-loop-based clock generators, i.e., no jitter accumulation, fast locking, stable loop operation, and easy integration of the loop filter. We propose a phase detector with a reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problems of the conventional DLL-based system. Fabricated in a 0.35-/spl mu/m CMOS process, our DLL-based clock generator occupies 0.07 mm/sup 2/ of area and consumes 42.9 mW of power. It operates in the frequency range of 120 MHz-1.1 GHz and has a measured cycle-to-cycle jitter of /spl plusmn/7.28 ps at 1 GHz. The die area, peak-to-peak, and r.m.s. jitter are the smallest compared to those of reported high-frequency clock multipliers.     

A packaged high-performance decision IC up to 45-Gb/s

A packaged D-type flip-flop (DFF) decision circuit for optical OC-768 systems and testing equipment is reported. The circuit uses 1 /spl mu/m InP SHBT technology featuring f/sub T//f/sub max/=150 GHz and has been operated up to 45 Gb/s with a clock phase margin about 180/spl deg/. Measured output eye diagrams from packaged devices exhibit 9/8 ps rise/fall with only 3ps peak-peak jitter. A single-ended AC-coupled clock input makes the application of this circuit very convenient. The IC dissipates 440 mW from a -4V supply voltage.     

10 GHz full-rate clock and data recovery circuit in 0.18 /spl mu/m CMOS without external reference clock

The design of a fully monolithic integrated 10 GHz full-rate clock and data recovery (CDR) circuit in 0.18 /spl mu/m digital CMOS technology, which employs an injection phase-locked loop (PLL) technique is presented. The CDR operating without the external reference exhibits a capture range of 200 MHz while consuming 205 mA current from 1.8 V supply including the output buffer. The recovered clock signal with 250 mV/sub pp/ pseudorandom bit Sequence input data of length 2/sup 31/-1 exhibits 7.9 ps of peak-to-peak (p-p) and 1.1 ps of root-mean-square (RMS) jitter. The measured clock phase noise at 1 MHz offset is approximately -109 dBc/Hz.     

A high-speed, low-power clock generator for a microprocessorapplication

This paper discusses the design of the clock generator for the Alpha 21264. As the speed performances are of primary concern in the whole design, the clock-generator jitter and phase misalignment must be as low as possible in a very noisy environment. A dedicated on-chip voltage regulator based on a bandgap reference has been designed to reduce the effect of supply noise on the clock generator. To avoid a large voltage drop across the power-supply bond wires during the startup sequence, the core frequency can be increased by steps in one period of the core clock, with a limited frequency overshoot and no missing pulses. The circuit has been implemented in a CMOS 0.35 μm process. The voltage-controlled-oscillator frequency range is between 350 MHz and 2.8 GHz, with a peak-to-peak cycle-to-cycle jitter lower than 16 ps. While booting Unix on a system, the maximum phase misalignment is lower than ±100 ps     

A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS

The implemented static frequency divider provides quadrature (Q) clock outputs and divides frequencies up to 44GHz. The core divider circuit consists of two current-mode logic (CML) latches and consumes 3.2mW from a 1.1-V supply. The divided outputs result in a peak-to-peak and rms jitter of 6.3 and 0.8ps, respectively, and the maximum phase mismatch between the in-phase (I) and Q-outputs amounts to 1ps at an input frequency of 40GHz. The high division frequency is achieved by employing resistive loads, inductive peaking, and optimizing the circuit layout for reduced parasitic capacitances in the latches. The core divider consumes a chip area of 30/spl mu/m/spl times/40/spl mu/m only.     

Injection-locked Fabry-Pe/spl acute/rot laser with electronic feedback for clock recovery from high-speed OTDM signals

We demonstrate the use of an injection-locked Fabry-Pe/spl acute/rot laser diode with electronic feedback for base-rate clock recovery in N/spl times/10 Gb/s optical time-division-multiplexing (OTDM) systems. Injection-locking enhances the resonance frequency of the laser and the electrical feedback achieves strong resonance at the base-rate frequency of the injected data streams, enabling ultrastable electrical clock signal generation at the base rate of 10 GHz. Experimental demonstrations for clock recovery at 10 GHz from 40-Gb/s OTDM data streams and 4-1 demultiplexing of the data using the extracted clock after fiber transmission is presented. The timing jitter measured in the recovered electrical clock is less than 0.25 ps.     

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm²     

An all-digital phase-locked loop for high-speed clock generation

An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-/spl mu/m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P/sub k/-P/sub k/ jitter of the output clock is <70 ps, and the root-mean-square jitter of the output clock is <22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.     

A portable clock multiplier generator using digital CMOS standardcells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps     

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.     

A low-jitter PLL clock generator for microprocessors with lockrange of 340-612 MHz

A fully integrated, phase-locked loop (PLL) clock generator/phase aligner for the POWER3 microprocessor has been designed using a 2.5-V, 0.40-μm digital CMOS6S process. The PLL design supports multiple integer and noninteger frequency multiplication factors for both the processor clock and an L2 cache clock. The fully differential delay-interpolating voltage-controlled oscillator (VCO) is tunable over a frequency range determined by programmable frequency limit settings, enhancing yield and application flexibility. PLL lock range for the maximum VCO frequency range settings is 340-612 MHz. The charge-pump current is programmable for additional control of the PLL loop dynamics. A differential on-chip loop filter with common-mode correction improves noise rejection. Cycle-cycle jitter measurements with the microprocessor actively executing instructions were 10.0 ps rms, 80 ps peak to peak (P-P) measured from the clock tree. Cycle-cycle jitter measured for the processor in a reset state with the clock tree active was 8.4 ps rms, 62 ps P-P. PLL area is 1040×640 μm². Power dissipation is <100 mW     

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-/spl mu/m CMOS technology in an area of 1.75/spl times/1.55 mm/sup 2/, the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10/sup -9/ with a pseudorandom bit sequence of 2/sup 23/-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.     

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment     

一种高性能小数级联型锁相环电路

提出了一种低抖动、高频率分辨率、快速锁定的小数级联型锁相环。采用倍乘型延迟锁定环和基于和差调制器(DSM)的相位选择器实现小数倍频,并通过级联一个高带宽的整数型锁相环抬升频率且实现对DSM量化噪声的进一步滤除。基于TSMC 65 nm CMOS工艺,面积为0.27 mm^(2),输出频率为1.064~1.936 GHz。通过电路仿真输入100 MHz参考频率,PLL的1.872 GHz输出频率在300 ns以内完成锁定,1.2 V电源电压下整体功耗为8.6 mW。此时频率分辨率约1 kHz,1 kHz~100 MHz的积分范围内均方根抖动为1.32 ps。     

A low-jitter mixed-mode DLL for high-speed DRAM applications

This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the level of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-μm triple-metal CMOS process and occupies a die area of 0.45 mm². Measured rms jitter is 6.38 ps. The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply     

A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump

A 0.5-5 GHz wide-range multiphase delay-locked loop (MDLL) with a calibrated charge pump is presented. A multiperiod-locked technique is used to enhance the input frequency range of a MDLL and avoid the harmonic-locked problem. The charge pump current is also calibrated to reduce the static phase error. This MDLL has been fabricated in 0.13- CMOS process. The measured root-mean-square and peak-to-peak jitters are 1.06 and 8 ps at 5 GHz, respectively. The power dissipation at 5 GHz is 36 mW for a supply voltage of 1.2 V.     

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the "limited pull-in range," and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.     

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS

This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-/spl mu/m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.     

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles.