基于Al2O3中间层的InP/SOI晶片键合技术研究

研究了基于Al2O3中间层的InP/SOI晶片键合技术.该方案利用原子层沉积技术在SOI晶片表面形成Al2O3作为InP/SOI键合中间层,同时采用氧等离子体工艺对晶片表面进行活化处理.原子力显微镜和接触角测试结果表明,氧等离子体处理使得晶片的表面特性更适于实现键合.透射电子显微镜和X射线能谱仪测试结果证实,采用Al2O3中间层可以实现InP晶片与SOI晶片的可靠键合.     

GaAs/InP低温晶片键合的研究

将硫脲溶液用于GaAs/InP基材料低温晶片键合的表面处理工艺,实现了GaAs/InP基材料间简单、无毒性的低温(380 ℃)晶片键合.并通过界面形貌,解理后断裂面,键合强度及键合界面I-V特性对键合晶片进行了分析.     

GaAs/Si直接键合用GaAs表面化学活化技术

研究了GaAs/Si疏水性直接键合技术中GaAs表面化学活化关键工艺,对比分析了不同体积分数的HF和HCl溶液作为表面活性处理剂时对GaAs表面进行活化处理的结果。发现用HCl和H2O溶液处理GaAs晶片得到的表面均方根粗糙度要优于用HF处理得到的结果,并且将处理过的GaAs晶片与Si片进行直接键合,发现用HCl进行表面活化的GaAs晶片与Si片键合的成功率要高于用HF进行表面活化的GaAs和Si键合。在200,300和400℃条件下,采用HCl和H2O体积比为1∶10的溶液处理的GaAs晶片与Si片都成功键合,并且200℃条件下键合后的界面质量较好。     

光路可调的红外透射方法检测键合质量

基于红外透射原理,采用调节光路的冷光源方法搭建了晶片键合界面的质量检测系统。利用该系统可以很好的实现GaAs,InP材料的键合界面检测和刀片分离时的在线监测,同时本文以GaAs基分布布拉格反射镜(DBR)和InP基有源区键合为例,结合红外透视图像和薄膜转移照片分析,对键合表面处理方法进行了优化选择。试验表明该检测系统数据可靠,使用方便,为晶片键合条件及参数优化提供了实用平台。     

基于硼酸溶液处理的GaAs/InP低温晶片键合技术

提出了一种基于硼酸溶液的GaAs/InP低温晶片键合技术,实现了GaAs/InP基材料间简单、无毒性的高质量、低温(290℃)晶片键合。GaAs/InP键合晶片解理截面的扫描电子显微镜(SEM)图显示,键合界面整齐,没有裂缝和气泡。通过键合过程,InP上的In0.53Ga0.47As/InP多量子阱结构转移到了GaAs基底上。X射线衍射及荧光谱显示,键合后的多量子阱晶体质量未变。二次离子质谱(SIMS)和Raman光谱图显示,GaAs/InP键合晶片的中间层厚度约为17 nm,界面处B元素有较高的浓度,键合晶片的中间层很薄,因此可以得到较好的电学、光学特性。     

表面活化处理在激光局部键合中的应用

为了研究低热应力键合工艺,提出了一种将表面活化直接键合与激光局部键合相结合的键合技术。首先采用RCA溶液对键合片进行表面亲水活化处理,并在室温下成功地完成了预键合。然后在不使用任何夹具施加外力辅助的情况下,利用波长1064nm、光斑直径500μm、功率70W的Nd:YAG连续式激光器,实现了激光局部键合,并取得了6.3MPa~6.8MPa的键合强度。结果表明,这种以表面活化预键合代替加压的激光局部键合技术克服了传统激光键合存在的激光对焦困难,以及压力不匀易损害键合片和玻璃盖板等缺点,同时缩短了表面活化直接键合的退火时间,提高了键合效率。     

基于亲水表面处理的GaAs/GaN晶片直接键合

对晶片进行亲水表面处理,在氮气保护下500℃热处理10min,成功实现GaAs与GaN晶片的直接键合,键合质量较好.扫描电子显微镜观测结果表明,键合界面没有空洞.光致发光谱观测结果表明,键合工艺对晶体内部结构的影响很小.可见光透射谱测试结果表明,键合界面具有良好的透光特性.GaAs与GaN晶片直接键合的成功,为实现GaAs和GaN材料的集成提供了实验依据.     

基于亲水表面处理的GaAs/GaN晶片直接键合

对晶片进行亲水表面处理,在氮气保护下500℃热处理10min,成功实现GaAs与GaN晶片的直接键合,键合质量较好.扫描电子显微镜观测结果表明,键合界面没有空洞.光致发光谱观测结果表明,键合工艺对晶体内部结构的影响很小.可见光透射谱测试结果表明,键合界面具有良好的透光特性.GaAs与GaN晶片直接键合的成功,为实现GaAs和GaN材料的集成提供了实验依据.     

GaAs/InP键合电学性质的研究

III-V族晶片键合技术对于光电器件的制备和实现光电集成有着重要意义,然而,对于键合界面的电学性质仍然研究较少。采用热电子发射理论,基于界面态能级在禁带中连续分布的假设,根据分布函数结合I-V测试曲线可建立键合结构的界面态计算模型。利用该模型对不同条件下键合的InP/GaAs电学性质做了分析比较,通过初始势垒的确定,计算并比较了各种键合条件下GaAs/InP键合时的界面电荷及界面态密度。实验及计算结果表明疏水处理表面550度条件下键合晶片对有更低的表面初始势垒和更少的界面态密度,因而具有更好的I-V特性。     

InP/Si键合界面热应力分析

从理论上分析了键合热应力产生的原因,在此基础上,采用双层条状金属热应力模型讨论InP/Si键合过程中应力的大小及分布情况.结果表明, 由剪切应力和晶片弯矩决定的界面正应力是晶片中心区域大面积键合失败的主要原因,同时InP/Si键合合适的退火温度应该在250～300 ℃.最后在300 ℃退火条件下很好地实现了InP/Si键合,界面几乎没有气泡,有效键合面积超过90%.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

直接键合四结GaAs太阳电池研究

晶圆直接键合技术由于能将表面洁净的两个晶圆集成到一起,从而可以用来制备晶格失配 III-V族多结太阳电池。为了制备GaInP/GaAs/InGaAsP/InGaAs四结太阳电池,需采用具有低电阻率的GaAs/InP键合界面,从而实现GaInP/GaAs和InGaAsP/InGaA上下两个子电池的电学导通。我们设计并研究了具有不同掺杂元素和掺杂浓度的三种键合界面,并采用IV曲线对其电学性质进行表征。此外,对影响键合界面质量的关键工艺过程进行了研究,主要包括表面清洗技术和键合参数优化,例如键合温度、键合压力和键合时间等。最终制备出的键合四结GaInP/GaAs/InGaAsP/InGaAs太阳电池在AM0条件下效率最高达33.2%。     

New layer transfers obtained by the SmartCut process

The SmartCut process was first developed to obtain silicon-on-insulator (SOI) materials. Now an industrial process, the main Unibond SOI-structure trends are reported in this paper. Many material combinations can be achieved by this process, because it appears to enable the generic development of new structures. Several of the new structures combining different materials and different bonding layers are described. These include SiGe and strained-Si films onto an oxidized Si wafer, silicon-on-insulating multilayer (SOIM) structures, and InP or 4H-SiC film transfers onto low-cost substrates via metallic or even refractory conductive-film bonding layers. More recently, an original bonding process based on mark patterning, wafer bonding, and layer transfer has been proposed to obtain structures in which the relative crystalline-axis orientations of both the film and the substrate can be controlled accurately. In this case, a SmartCut process that includes a mark-patterning step appears well suited for precise control of axis orientations. A procedure is described to obtain an ultra-thin Si film bonded onto a Si wafer. An example of a pure screw-dislocation network achieved by the mark patterning, bonding, and layer-transfer process is reported in this paper. The results have important implications for nanostructure development.     

Compact and Highly Efficient Grating Couplers Between Optical Fiber and Nanophotonic Waveguides

We present high-efficiency grating couplers for coupling between a single-mode fiber and nanophotonic waveguides, fabricated both in silicon-on-insulator (SOI) and InP membranes using BenzoCycloButene wafer bonding. The coupling efficiency is substantially increased by adding a gold bottom mirror to the structures. The measured coupling efficiency to fiber is 69% for SOI grating couplers and 56% for bonded InP membrane grating couplers     

界面热应力对InP/Si键合质量的影响

通过实验和理论计算,分析了InP/Si键合过程中,界面热应力的分布情况、影响键合结果的关键应力因素及退火温度的允许范围。分析结果表明,由剪切应力和晶片弯矩决定的界面正应力是晶片中心区域大面积键合失败的主要原因,为保证良好的键合质量,InP/Si键合退火温度应该在300～350℃范围内选取。具体实验验证表明,该理论计算值与实验结果相一致。最后,在300℃退火条件下,很好地实现了2inInP/Si晶片键合,红外图像显示,界面几乎没有空洞和裂隙存在,有效键合面积超过90%。     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

Wafer-scale 3D integration of InGaAs photodiode arrays with Si readout circuits by oxide bonding and through-oxide vias

A new wafer-scale three dimensional (3D) integration technique, originally developed for Si, is applied to hybridize InP-based photodiode arrays with Si readout circuits. The infrared (IR) photodiodes consisted of an InGaAs absorption layer grown on the InP substrate and were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits to allow 3D integration in the Si fabrication facility. The finished 150-mm-diameter InP wafer was directly bonded to the SOI wafer and interconnected to the Si readout circuits by through-oxide vias (TOV). A 32 × 32 array with 6-μm pixel size was demonstrated. The 3D integration of InP with Si wafers achieved the smallest pixel size, which is less than a half of that can be achieved using conventional flip-chip bump bonding technique.