VLSI集成电路参数成品率及优化研究进展

VLSI的参数成品率是与制造成本和电路特性紧密相关的一个重要因素，随着集成电路(IC)进入超深亚微米发展阶段，芯片工作速度不断增加，集成度和复杂度提高，而工艺容差减小的速度跟不上这种变化，因此参数成品率的研究越来越重要．本文系统地讨论了参数成品率的模型和设计技术研究进展，分析不同技术的特点和局限性．最后提出了超深亚微米(VDSM)阶段参数成品率设计和成品率增强面临的主要问题及发展方向．     

VLSI中互连线工艺变化的若干问题研究进展

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,互连线的工艺变化已成为影响集成电路性能的重要因素.针对该问题,结合作者的研究工作,综述了目前国内外互连线工艺变化若干关键问题的研究进展情况,重点介绍工艺变化条件下互连线寄生电参数及其传输性能的研究方法,并分析不同技术的特点和局限性.最后展望了互连线工艺变化问题今后的研究发展方向.     

超深亚微米集成电路互连线几何变异提取方法

硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键.这里基于电阻和电容等电学测试结构相应的数学计算公式,阐述进行互连线几何变异提取的方法,分析所采用的测试结构与计算公式的可行性,讨论误差来源,提出仿真工作与测试芯片设计原则.目的在于解决工艺建模与寄生参数建模过程中电阻和电容变异之间紧密的空间相关性,从而易于建立用于集成电路参数成品率评估计算的可制造性设计模型.     

EDA技术与FPGA设计应用

EDA技术是现代电子设计技术的核心，它在现代集成电路设计中占据重要地位。随着深亚微米与超深亚微米技术的迅速发展，FPGA设计越来越多地采用基于VHDL的设计方法及先进的EDA工具。本文详细阐述了EDA技术与FPGA设计应用。     

深亚微米SOI工艺ESD防护器件设计

在集成电路设计领域,绝缘体上硅(SOI)工艺以其较小的寄生效应、更快的速度,得到广泛应用.但由于SOI工艺器件的结构特点及自加热效应(SHE)的影响,其静电放电(ESD)防护器件设计成为一大技术难点.当工艺进入深亚微米技术节点,基于部分耗尽型SOI(PD-SOI)工艺的ESD防护器件设计尤为困难.为了提高深亚微米SOI...     

测试与可测试性设计发展的挑战

CMOS器件进入超深亚微米阶段,集成电路(IC)继续向高集成度、高速度、低功耗发展,使得IC在测试和可测试性设计上都面临新的挑战.本文首先介绍了测试和可测试性设计的概念,分析了测试和可测试性设计面临的困境;然后讨论了系统芯片设计中的测试和可测试性设计,最后对测试和可测试性设计的未来发展方向进行了展望.     

可编程逻辑器件设计新思路

可编程逻辑器件在集成电路的发展中占有重要地位。深亚微米与超深亚微米技术的发展使可编程逻辑器件向系统级可编程芯片转移。本文详细阐述了基于IP的系统级可编程芯片的设计策略。     

可编程系统芯片（SOPC）发展策略

深亚微米技术和超深亚微米技术的发展使电子工业正在向可编程系统芯片（SOPC）设计转移。针对SOPC全新的设计流程，本文提出了基于IP的SOPC设计集成平台概念和设计策略，以及基于FPGA/CPLD的SOPC实现方案。     

基于TCAD工具的超突变结变容二极管设计

根据超突变结变容二极管设计和工艺特点,报道了利用SILVACO公司工艺模拟软件Athena、器件模拟软件Atlas等完成超突变结变容二极管的几何结构、浓度分布、工艺参数、电学参数等的设计,根据设计参数通过某型号Si超突变结变容二极管生产情况验证设计参数和电参数的吻合情况,改进实际工艺参数和模拟参数的容差系数;分别利用离子注入-扩散法和双离子注入法完成器件工艺制作,提高了的工艺重复性和成品率.采用TCAD技术大大缩短了研制周期、降低了费用.     

两相邻耦合RC互连的串扰效应及其抑制

随着微电子技术的进步,集成电路的特征尺寸逐步缩小,IC设计已经向着深亚微米甚至超深亚微米设计发展,一系列由于互连线引起的信号完整性问题需要设计者更多的考虑,互连线串扰已经成为影响IC设计成功与否的一个重要因素。针对串扰这一问题本文讨论了串扰对于电路的影响,分析了深亚微米集成电路设计中对两相邻耦合RC互连串扰的成因,介绍了互连线R,C参数的提取。以反相器驱动源和容性负载为例,建立了两相邻等长平行互连线的10阶互连模型,并且针对该模型,利用Cadence软件进行仿真,分析了引起串扰的因素。在此基础上,最后给出了有效抑制串扰的方法。     

The effect of dynamic design processing for yield enhancement inthe fabrication of deep sub-micron MOSFET's

With the downscaling of microelectronic devices, tighter process control and more elaborate fabrication equipment need to be complemented by process correcting techniques if good quality and high yields are to be expected. Dynamic design processing-a forward correcting technique by which some recipe values are recalculated during manufacturing-is such a technique. In this paper the effect of dynamic design processing on deep sub-micron MOSFET's is presented. The results show that a parametric yield improvement in excess of 25% over conventional manufacturing can be achieved     

Performance-Optimized Design for Parametric Reliability

Process variations have a significant impact on behavior of integrated circuits (ICs) designed in deep sub-micron (DSM) technologies, and it has been estimated that in some cases up to a generation of performance can be lost due to process variations (Bowman et al., IEEE J Solid State Circuits 37:183–190, 2002), making it a significant problem for design and manufacture of DSM ICs. Adaptive design techniques are fast evolving as a potential solution to this problem. Such techniques facilitate reconfiguration of an IC to enable its operation across process corners, thus ensuring parametric reliability in such ICs, and also improving manufacturing yield. In this paper, adaptive design techniques with a focus on timing of ICs, i.e., performance-optimized adaptive design, are explored. The focus of such performance-optimized adaptive design techniques is to ensure that adaptation does not cause an IC to violate timing specifications, thus giving priority to performance, which remains one of the most important parameters of an IC.     

深亚微米CMOS器件建模与BSIM模型

介绍了深亚微米CMOS器件基于电荷模型、基于表面势模型和基于电导模型的建模方法及其优缺点,并以BSIM系列模型为例,讨论了BSIM系列模型特点及半导体工艺发展对CMOS器件建模方法的影响。     

深亚微米集成电路中的ESD保护问题

本文对深亚微米工艺所引起的集成电路抗静电能力下降的原因和传统保护电路设计的缺陷进行了深入的阐述,从制造工艺、保护电路元件和保护电路结构三方面对深亚微米集成电路中的ESD 保护改进技术进行了详细论述     

一种新的用于RFIC ESD保护的双槽LVTSCR

低压触发硅控整流器件（Low-Voltage Triggering Silicon-controlled Rectifier,LVTSCR）由于具有高的放电效率和低的寄生参数,在ESD防护方面存着诸多优势,尤其对于深亚微米集成电路和高频应用领域。本文对影响LVTSCR回退（snapback）特性曲线的几个重要因素和它的配置方式作了详细的分析和评价,这些参数包括阳极串联电阻、栅电压以及器件的结构和尺寸。并且提出了一种双槽LVTSCR结构,该结构可以获得较高且容易调节的维持电压,从而使其snapback特性很好地符合ESD设计窗口规则。论文的最后讨论了RFIC中采用LVTSCR的ESD保护策略。     

深亚微米结构下的IC设计的电磁干扰（EMI）问题

在深亚微米结构下,集成电路IC的线路延迟和电磁干扰现象对于系统的影响更加突出,尤其是对超大规模集成（VLSI）电路系统。本文仅就深亚微米结构下IC设计的电磁干扰问题,详细分析了其产生的主要来源：宇宙射线、噪声干扰和静电放电ESD．以及预防措施。     

SOC基于LFSR的混合模式测试

随着集成电路深亚微米制造技术和设计技术迅速发展,系统芯片(SOC)作为一种解决方案得到了越来越广泛的应用。SOC的测试中,内建自测试(Built.In Self-Test,BIST)成为人们研究的热点。文中对SOC的设计特点及其BIST中的混合模式测试进行了探讨。     

Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing

Semiconductor testing is aimed at screening fabrication defects that impact expected functionality. While catastrophic defects result in non working devices, parametric faults result in marginalities and are of increasing concern with deep sub-micron process technologies. This work presents a scheme to monitor Circuit-Under-Test (CUT) static bias current to identify catastrophic as well as parametric faults. All circuits require a deterministic amount of DC bias current which may vary outside the specifications when faults exist within the circuit. We propose a compensated current measurement Built-in-Current-Sensor (BICS) scheme, which can be used for sub-system level/circuit-level bias current measurements. The BICS provides accessibility to internal blocks and enables isolated parametric testing. Calibration routine enables process independence and provides robustness. The BICS is compatible with Very-Low-Cost Automatic Test Equipment (VLC-ATE), and can be used for detailed parametric testing in the production environment.     

等离子体工艺引起的MOSFET栅氧化层损伤

在深亚微米 MOS集成电路制造中 ,等离子体工艺已经成为主流工艺。而等离子体工艺引起的栅氧化层损伤也已经成为限制 MOS器件成品率和长期可靠性的一个重要因素。文中主要讨论了等离子体工艺引起的充电损伤、边缘损伤和表面不平坦引起的电子遮蔽效应的主要机理 ,并在此基础上讨论了减小等离子体损伤的有效方法。     

Analysis of Cu/Low-k structure under back end of line process

As the progress of the semiconductor process develops to achieve miniaturization and attain better performances for the electronic device, next-generation IC chips with deep sub-micron Cu/low-k stacked structures adopting the fabrication of (dual) damascene are developed to meet the urgent requirements of reducing high RC delay; the purpose of this is to obtain high-speed signal communication. However, due to poor adhesion and intrinsically lower fracture toughness of low-k materials as well as process loading that introduces flaws and delaminations, the phenomenon of crack growth is observed. To investigate the large scale difference problem, such as the back end of line (BEoL) structure to the silicon chip, a special multi-scale finite element simulation technology, global-local finite element method, is used to deal with this issue. The interfacial crack in the BEoL structure is modeled using the global-local technique. The chemical vapor deposition (CVD) process that induced loading to a micro crack in the interface between etch stop layer and metal track layer (ESL/Mx interface) will also be discussed through a statistical factorial design method in order to understand the crack growth phenomena that might occur during the BEoL process.