Effect of primary creep and plasticity in the modeling of thermal fatigue of SnPb and SnAgCu solder joints

It has been conventional to simplify the thermo-mechanical modeling of solder joints by omitting the primary (transient) contributions to total creep deformation, assuming that secondary (steady-state) creep strain is dominant and primary creep is negligible. The error associated with this assumption has been difficult to assess because it depends on the properties of the solder joint and the temperature–time profile. This paper examines the relative contributions of plasticity, primary and secondary creep in Sn40Pb and Sn3.8Ag0.7Cu solders using the analysis of a trilayer solder joint structure with finite elements and a newly developed finite difference technique. The influences of temperature amplitude and ramp rate have been quantified. It was found that for the thermal profiles considered, the role of plasticity was negligible for trilayer assemblies with SnPb and SnAgCu solder interlayers. Furthermore, when primary creep was included for SnAgCu, the temperature-dependent yield strength was not exceeded and no plastic strains resulted. Neglect of primary creep can result in errors in the predicted stress and strain of the solder joint. Damage metrics based on the stabilized stress vs. strain hysteresis loop, for symmetric 5 min upper/lower dwell periods, differ widely when primary creep is considered compared to the secondary-only creep model. Creep strain energy density differences between the secondary-only and primary plus secondary creep models for SnPb were 32% (95 °C/min–Δ165 °C thermal profile), 32% (95 °C/min–Δ100 °C) and 35% (14 °C/min–Δ100 °C); similarly for SnAgCu, the differences were 29% (95 °C/min–Δ165 °C), 46% (95 °C/min–Δ100 °C) and 58% (14 °C/min–Δ100 °C). Accumulated creep strain differences between the secondary-only and primary plus secondary creep models for SnPb were 21% (95 °C/min–Δ165 °C), 25% (95 °C/min–Δ100 °C) and 25% (14 °C/min–Δ100 °C); similarly for SnAgCu the differences were 82% (14 °C/min–Δ100 °C), 89% (95 °C/min–Δ100 °C) and 100% (95 °C/min–Δ165 °C). In turn, these discrepancies can lead to errors in the estimation of the solder thermal fatigue life due to the changing proportion of primary creep strain to total inelastic strain under different thermal profiles, particularly for SnAgCu.     

Effects of process conditions on reliability, microstructure evolution and failure modes of SnAgCu solder joints

In this study, microstructure evolution at intermetallic interfaces in SnAgCu solder joints of an area array component was investigated at various stages of a thermal cycling test. Failure modes of solder joints were analyzed to determine the effects of process conditions on crack propagation. Lead-free printed-circuit-board (PCB) assemblies were carried out using different foot print designs on PCBs, solder paste deposition volume and reflow profiles. Lead-free SnAgCu plastic-ball-grid-array (PBGA) components were assembled onto PCBs using SnAgCu solder paste. The assembled boards were subjected to the thermal cycling test (−40 °C/+125 °C), and crack initiation and crack propagation during the test were studied. Microstructure analysis and measurements of interface intermetallic growth were conducted using samples after 0, 1000, 2000 and 3000 thermal cycles. Failures were not found before 5700 thermal cycles and the characteristic lives of all solder joints produced using different process and design parameters were more than 7200 thermal cycles, indicating robust solder joints produced with a wide process window. In addition, the intermetallic interfaces were found to have Sn–Ni–Cu. The solder joints consisted of two Ag–Sn compounds exhibiting unique structures of Sn-rich and Ag-rich compounds. A crystalline star-shaped structure of Sn–Ni–Cu–P was also observed in a solder joint. The intermetallic thicknesses were less than 3 μm. The intermetallics growth was about 10% after 3000 thermal cycles. However, these compounds did not affect the reliability of the solder joints. Furthermore, findings in this study were compared with those in previous studies, and the comparison proved the validity of this study.     

CCGA packages for space applications

Commercial-off-the-shelf (COTS) area array packaging technologies in high reliability versions are now being considered for applications, including use in a number of NASA electronic systems being utilized for both the Space Shuttle and Mars Rover missions. Indeed, recently a ceramic package version specifically tailored for high reliability applications was used to provide the processing power required for the Spirit and Opportunity Mars Rovers built by NASA-JPL. Both Rovers successfully completed their 3-months mission requirements and continued exploring the Martian surface for many more moths, providing amazing new information on previous environmental conditions of Mars and strong evidence that water exists on Mars.Understanding process, reliability, and quality assurance (QA) indicators for reliability are important for low risk insertion of these newly available packages in high reliability applications. In a previous investigation, thermal cycle test results for a non-functional daisy-chained peripheral ceramic column grid array (CCGA) and its plastic ball grid array (PBGA) version, both having 560 I/Os, were gathered and are presented here. Test results included environmental data for three different thermal cycle regimes (−55/125 °C, −55/100 °C, and −50/75 °C). Detailed information on these—especially failure type for assemblies with high and low solder volumes—are presented. The thermal cycle test procedure followed those recommended by IPC-9701 for tin–lead solder joint assemblies. Its revision A covers guideline thermal cycle requirements for Pb-free solder joints. Key points on this specification are also discussed.In a recent investigation a fully populated CCGA with 717 I/Os was considered for assembly reliability evaluation. The functional package is a field-programmable gate array that has much higher processing power than its previous version. This new package is smaller in dimension, has no interposer, and has a thinner column wrapped with copper for reliability improvement. This paper will also present thermal cycle test results for assemblies of this and its plastic package version with 728 I/Os, both of which were exposed to four different cycle regimes. Two of these cycle profiles are specified by IPC-9701A for tin–lead, namely, −55 to 100 °C and −55 to 125 °C. One is a cycle profile specified by Mil-Std-883, namely, −65/150 °C, generally used for ceramic hybrid packages screening and qualification. The last cycle is in the range of −120 to 85 °C, a representative of electronic systems directly exposed to the Martian environment without use in a thermal control enclosure. Per IPC-9701A, test vehicles were built using daisy chain packages and were continuously monitored and/or manually checked for opens at intervals. The effects of many process and assembly variables—including corner staking commonly used for improving resistance to mechanical loading such as drop and vibration loads—were also considered as part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples of these are presented along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages.     

The effect of solder paste composition on the reliability of SnAgCu joints

As the electronics industry is moving towards lead-free manufacturing processes, more effort has been put into the reliability study of lead-free solder materials. Various tin–silver–copper-based solders have become widely accepted alternatives for tin–lead solders. In this study, we have tested three different SnAgCu solder compositions. The first consisted of a hypoeutectic 96.5Sn/3.0Ag/0.5Cu solder, the second of a eutectic 95.5Sn/3.8Ag/0.7Cu solder, and the third of a hypereutectic 95.5Sn/4.0Ag/0.5Cu solder. A eutectic SnPb solder was used as a reference. The test boards were temperature-cycled (−40 to +125 °C) until all samples failed. The results of the temperature cycling test were analyzed, and cross-section samples were made of the failed joints. Scanning electron and optical microscopy were employed to analyze the fracture behavior and microstructures of the solder joints. The reliability of lead-free solders and the effect of microstructures on joint reliability are discussed.     

Effect of different temperature cycling profiles on the crack initiation and propagation of Sn–3.5Ag wave soldered solder joints

Temperature cycling of a test board with different electronic components was carried out at two different temperature profiles in a single-chamber climate cabinet. The first temperature profile ranged between −55 and 100 °C and the second between 0 and 100 °C. Hole mounted components and secondary side SMD components were wave soldered with an Sn–3.5Ag alloy. Joints of both dual in line (DIL) packages and ceramic chip capacitors were investigated. Crack initiation and propagation was analysed after every 500 cycles. In total, 6500 cycles were run at both temperature profiles and the observations from each profile were compared.For both kinds of components analysed, cracks were first visible for the temperature profile ranging between −55 and 100 °C. For this temperature profile, and for DIL packages, cracks were visible already after 500 cycles, whereas for the other temperature profile, cracks initiated between 1000 and 1500 cycles. The cracks observed after 1500 cycles were visibly smaller for the temperature profile ranging between 0 and 100 °C, concluding that crack initiation and propagation was slightly slower for this temperature profile. For the chip capacitors, cracks were first visible after 2000 cycles.     

Thermally induced deformation of solder joints in real packages: Measurement and analysis

The paper presents a hybrid experimental and analytical approach to track the deformation of solder joints in an electronic package subject to a thermal process. The solder joint strain is directly measured using a computer vision technique. The strain measurement is analyzed following an approach that is devised based on an established solder constitutive relation. The analysis leads to the determination of the solder joint stress and in turn, to the separation of the elastic, plastic and creep strain from the measured total strain. The creep strain rate and stress–strain hysteresis loop are also obtained. Two case studies are presented to illustrate the applications and to show the viability of the approach. Each case involves a resistor package with SAC (Sn95.5Ag3.8Cu0.7) solder joints, which is subjected to a temperature variation between ambient and 120 °C. The results confirm that shear is a dominant strain component in such solder joints. The shear strain varies nearly in phase with the temperature whereas the shear stress exhibits a different trend of variation due to stress relaxation. The peak shear stress of around 10 MPa to 15 MPa are found, which occur at near 70 °C in both cases, when the temperature ramps up at approximately 3 °C/min. The creep shear strain goes up to 0.02 and accounts for over 80% of the total shear strain. The creep strain rate is in the order of magnitude of 10⁻⁵ s⁻¹. Responding to the temperature cycling with such moderate rate, the creep strain shows modest ratcheting while the stress–strain hysteresis stabilizes in two cycles.     

Creep of thermally aged SnAgCu-solder joints

The creep behaviour of Sn96.5Ag3.5- and Sn95.5Ag3.8Cu0.7-solder was studied specifically for its dependence on technological and environmental factors. The technological factors considered were typical cooling rates and pad metallizations for solder joints in electronic packaging. The environmental factors included microstructural changes as a result of thermal aging of solder joints. Creep experiments were conducted on three types of specimens—flip–chip joints, PCB solder joints and bulk specimens. flip–chip specimens were altered through the selection of various under bump metallizations (Cu vs. NiAu), cooling rates (40 K/min vs. 120 K/min), and thermal storage (24 h, 168 h, and 1176 h at 125 °C). PCB solder joints were studied by using a copper pin soldered into a thru-hole connection on a printed circuit board having a NiAu metallization. Bulk specimens contained the pure alloys. The creep behaviour of the SnAg and SnAgCu solders varied in dependence of specimen type, pad metallization and aging condition. Constitutive models for SnAg and SnAgCu solders as they depend on the reviewed factors are provided.     

Effects of TMF heating rates on damage accumulation and resultant mechanical behavior of Sn–Ag based solder joints

Solder joint reliability depends on several service parameters such as temperature extremes encountered, dwell times at these temperatures, and the ramp-rates representing the rate at which the temperature changes are imposed. TMF of Sn–Ag based solder alloy joints of realistic dimensions were carried out with dwell of 115 min and 20 min at 150 °C and −15 °C, respectively. Different heating rates were obtained by controlling the power input during heating part of TMF cycles. Surface damage and residual mechanical strength of these solder joints were characterized after 0, 250, 500, and 1000 TMF cycles to evaluate the role of TMF heating rate on the solder joint integrity.     

Microstructure and creep behaviour of eutectic SnAg and SnAgCu solders

The paper presents creep data, that was gained on specimens of different microstructures. The three specimen types have been flip chip solder joints, pin trough hole solder joints and standard bulk solder specimens. The bulk solder specimen was a dog-bone type specimen (diameter=3 mm, LENGTH=117 mm). The pin trough hole solder joint consisted on a copper wire that was soldered into a hole of a double sided printed circuit board (thickness 1.5 mm). The flip chip solder joint specimen consisted of two silicon chips (4 mm × 4 mm), which were connected by four flip chip joints (one on each corner). SnAg and SnAgCu flip chip bumps (footprint 200 μm × 200 μm, joint height 165–200 μm, centre diameter 90…130 μm) were created by printing solder paste.Constant–load creep tests were carried out on all three specimen types at temperatures between 5 and 70 °C. Creep data was taken for strain rates between 10⁻¹⁰ and 10⁻³ s⁻¹. The specimens were tested in “as cast” condition and after thermal storage.The microstructural properties of the bulk specimens and real solder joints were examined using metallographic sectioning, optical microscopy techniques, and SEM-microprobe analysis. The results of the microstructural analysis were related to the investigated mechanical properties of the solders. Models of SnAg3.5 and SnAg4Cu0.5, that can be used with the ANSYS FEM software package, will be presented.     

Properties of low temperature Sn–Ag–Bi–In solder systems

The metallurgical and mechanical properties of Sn–3.5 wt%Ag–0.5 wt%Bi–xwt%In (x = 0–16) alloys and of their joints during 85 °C/85% relative humidity (RH) exposure and heat cycle test (−40–125 °C) were evaluated by microstructure observation, high temperature X-ray diffraction analysis, shear and peeling tests. The exposure of Sn–Ag–Bi–In joints to 85 °C/85%RH for up to 1000 h promotes In–O formation along the free surfaces of the solder fillets. The 85°C/85%RH exposure, however, does not influence the joint strength for 1000 h. Comparing with Sn–Zn–Bi solders, Sn–Ag–Bi–In solders are much stable against moisture, i.e. even at 85 °C/85%RH. Sn–Ag–Bi–In alloys with middle In content show severe deformation under a heat cycles between −40 °C and 125 °C after 2500 cycles, due to the phase transformation from β-Sn to β-Sn + γ-InSn₄ or γ-InSn₄ at 125 °C. Even though such deformation, high joint strength can be maintained for 1000 heat cycles.     

Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling

Growth behavior of tin whiskers from pure tin and tin–bismuth plated leadframe (LF) packages for elevated temperature and high humidity storages and during thermal cycling was observed. In the storage at 60 °C/93% relative humidity (RH) and 85 °C/85%RH the galvanic corrosion occurred at the outer lead toes and shoulders where the base LF material is exposed, forming tin oxide layers of SnO₂. The corroded layers spread inside the film and formed whiskers around the corroded islands. Many whiskers were observed to grow from grain boundaries for the Fe–42Ni alloy (alloy42) LF packages. It was confirmed that the corrosion tends to occur on the side surfaces of outer leads adjacent to the mold flash. The contribution of ionic contaminants in epoxy mold compound (EMC) to the corrosion was not identified. During thermal cycling between −65 °C and +150 °C whiskers grew out of as-deposited grains for pure tin-plated alloy42 LF packages and they grew linearly with an increase of number of cycle. Growth mechanisms of the whiskers from grain boundaries and as-deposited grains were discussed from the deformation mechanism map for tin and mathematical calculation with a steady-state diffusion model.     

Ball grid array reliability assessment for aerospace applications

Reliability of ball grid arrays (BGAs) was evaluated with special emphasis on space applications. This work was performed as part of a consortium led by the Jet Propulsion Laboratory (JPL) to help build the infrastructure necessary for implementing this technology. Nearly 200 test vehicles, each with four package types, were assembled and tested using an experiment design. The most critical variables incorporated in this experiment were package type, board material, surface finish, solder volume, and environmental condition. The packages used for this experiment were commercially available packages with over 250 I/Os including both plastic and ceramic BGA packages.The test vehicles were subjected to thermal and dynamic environments representative of aerospace applications. Two different thermal cycling conditions were used, the JPL cycle ranged from −30°C to 100°C and the Boeing cycle ranged from −55°C to 125°C. The test vehicles were monitored continuously to detect electrical failure and their failure mechanisms were characterized. They were removed periodically for optical inspection, scanning electron microscopy (SEM) evaluation, and cross-sectioning for crack propagation mapping. Data collected from both facilities were analyzed and fitted to distributions using the Weibull distribution and Coffin–Manson relationships for failure projection. This paper will describe experiment results as well as those analyses.     

Electromigration of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite flip–chip solder bumps with Ti/Ni(V)/Cu under bump metallurgy

We examine electromigration fatigue reliability and morphological patterns of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite solder bumps in a flip–chip package assembly with Ti/Ni(V)/Cu UBM. The flip–chip test vehicle was subjected to test conditions of five combinations of applied electric currents and ambient temperatures, namely, 0.4 A/150 °C, 0.5 A/150 °C, 0.6 A/125 °C, 0.6 A/135 °C, and 0.6 A/150 °C. The electrothermal coupling analysis was employed to investigate the current crowding effect and maximum temperature in the solder bump in order to correlate with the experimental electromigration reliability using the Black’s equation as a reliability model. From available electromigration reliability models, we also present a comparison between fatigue lives of Sn–37Pb solder bumps with Ti/Ni(V)/Cu and those with Al/Ni(V)/Cu UBM under different current stressing conditions.     

Thermal fatigue endurance of collapsible 95.5Sn4Ag0.5Cu spheres in LTCC/PWB assemblies

The behavior of thermomechanically loaded collapsible 95.5Sn4Ag0.5Cu spheres in LTCC/PWB assemblies with high (LTCC/FR-4; ΔCTE 10 ppm/°C) and low (LTCC/Arlon; ΔCTE < 10 ppm/°C) global thermal mismatches was studied by exposing the assemblies into two thermal cycling tests. The characteristic lifetimes of the LTCC/FR-4 assemblies, tested over the temperature ranges of 0–100 °C and −40 to 125 °C, were 1475 and 524 cycles, respectively, whereas the corresponding values of the LTCC/Arlon assemblies were 5424 and 1575 cycles. According to the typical requirements for the industrial lifetime duration of solder joints, the former values are inadequate, whereas the latter are at an acceptable level in a few cases. Furthermore, the global thermal mismatch affected the thermal fatigue behavior of the 95.5Sn4Ag0.5Cu spheres in the temperature range of −40 to 125 °C.     

Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling

Growth behavior of tin whiskers from pure tin and tin-bismuth plated leadframe (LF) packages for elevated temperature and high humidity storages and during thermal cycling was observed. In the storage at 60 °C/93% relative humidity (RH) and 85 °C/85%RH the galvanic corrosion occurred at the outer lead toes and shoulders where the base LF material is exposed, forming tin oxide layers of SnO₂. The corroded layers spread inside the film and formed whiskers around the corroded islands. Many whiskers were observed to grow from grain boundaries for the Fe–42Ni alloy (alloy42) LF packages. It was confirmed that the corrosion tends to occur on the side surfaces of outer leads adjacent to the mold flash. The contribution of ionic contaminants in epoxy mold compound (EMC) to the corrosion was not identified. During thermal cycling between −65 °C and +150 °C whiskers grew out of as-deposited grains for pure tin plated alloy42 LF packages and they grew linearly with an increase of number of cycle. Growth mechanisms of the whiskers from grain boundaries and as-deposited grains were discussed from the deformation mechanism map for tin and mathematical calculation with a steady-state diffusion model.     

Temperature profile effects in accelerated thermal cycling of SnPb and Pb-free solder joints

Accelerated thermal cycling (ATC) has been widely used in the microelectronics industry for reliability assessment. ATC testing decreases life cycle test time by one or more of the following means: increasing the heating and cooling rate, decreasing the hold time, or increasing the range of the applied temperature. The relative effect of each of these cycle parameters and the failure mechanisms they induce has been the subject of many studies; however uncertainty remains, particularly regarding the role of the heating and cooling rate. In this research, three conditions with two ramp rates (14 °C/min and 95 °C/min) and two temperature ranges (ΔT = 0–100 °C and −40 to 125 °C) were applied to resistor 2512 and PBGA 256 test vehicles assembled with SnPb and Pb-free solders. The test results showed that the higher ramp rate reduced the testing time while retaining the same failure modes, and that the damage per cycle increased with the temperature difference. For the resistors, the Pb-free solder joints lasted longer than the SnPb joints at the smaller ΔT, but were inferior at the larger ΔT. In contrast, the Pb-free solder joints in the PBGA test vehicles lasted longer than the SnPb solder under both conditions.     

Board level reliability assessment of chip scale packages

A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.     

Lead-free 0201 manufacturing, assembly and reliability test results

The trend towards smaller, faster and cheaper electronic devices has led to an increase in the use of 0201 (L  0.02 in.; W  0.01 in.) and even smaller sized passive components. The size advantages of the 0201 component make it a popular choice among design engineers but not among manufacturing engineers. From a manufacturing perspective, the size of the 0201 package poses significant challenges to the printed circuit board (PCB) assembly process. The many challenges with 0201 assembly can be attributed to the solder paste volume, pad design, aperture design, board finish, type of solder paste, pick-and-place and reflow profile. If these factors are not optimized, they will introduce undesirable manufacturing defects. The small size of 0201 packages and undetected manufacturing defects will also raise concerns about their second level interconnect reliability, especially for lead-free solder alloys and surface finishes, with new processes and higher reflow requirements. To determine the optimum conditions, a design-of-experiment (DOE) study was carried out to investigate the effects of these parameters on assembly defects and solder joint reliability.This paper presents the test results and comparative literature data on the influence of a few key manufacturing parameters and defects associated with the 0201 component using lead-free and tin–lead solder alloys. Data pertaining to component shear strength before and after isothermal aging at 150 °C and intermetallic growth up to 500 h of aging are presented. A number of test vehicles were also subjected to thermal cycling (1500 cycles) in the range of −55/100 °C to determine the solder fatigue behavior. Shear test results for test vehicles subjected to thermal cycling is also presented. In addition, optical microscopy analysis of solder joint behavior during thermal cycling showing the progress of the solder damage and cross-sectional photos taken at 1500 cycles is included.     

Solder joint reliability evaluation of chip scale package using a modified Coffin–Manson equation

Thermal cycle tests were performed for chip scale package (CSP) solder joints with Sn–37mass%Pb under several thermal cycle conditions. Under the conventional thermal cycle conditions, which heat up to approximately 100 °C, microstructure coarsening occurred and solder joints were fractured. The thermal fatigue lives followed the modified Coffin–Manson equation. The exponential factors m and n, and the activation energy Q in that equation were evaluated as 0.33, −1.9 and 15.5 kJ/mol, respectively. When the maximum temperature is room temperature and the temperature range is very narrow, the solder joint fracture occurred without microstructure coarsening, and the thermal fatigue life does not follow the modified Coffin–Manson equation.     

Pb-free high temperature solders for power device packaging

Reliabilities of joints for power semiconductor devices using a Bi-based high temperature solder has been studied. The Bi-based solder whose melting point is 270 °C were prepared by mixing of the CuAlMn particles and molten Bi to overcome the brittleness of Bi. Then, joined samples using the solder were fabricated and thermal cycling tests were examined. After almost 2000 test cycles of −40/200 °C test, neither intermetallic compounds nor cracks were observed for CTE (Coefficient of Thermal Expansion) matched sample with Cu interface. On the other hand, certain amount of intermetallic compound such as Bi₃Ni was found for a sample with Ni interface. In addition, higher reliability of this solder than Sn-Cu solder was obtained after −40/250 °C test. Furthermore, an example power module structure using double high temperature solder layers was proposed.