NN based ATM cell scheduling with queue length-based priorityscheme

The asynchronous transfer mode (ATM) is the choice of transport mode for broadband integrated service digital networks (B-ISDNs). We propose a window-based contention resolution algorithm to achieve higher throughput for nonblocking switches in ATM environments. In a nonblocking switch with input queues, significant loss of throughput can occur due to head-of-line (HOL) blocking when first-in first-out (FIFO) queueing is employed. To resolve this problem, we employ bypass queueing and present a cell scheduling algorithm which maximizes the switch throughput. We also employ a queue length based priority scheme to reduce the cell delay variations and cell loss probabilities. With the employed priority scheme, the variance of cell delay is also significantly reduced under nonuniform traffic, resulting in lower cell loss rates (CLRs) at a given buffer size. As the cell scheduling controller, we propose a neural network (NN) model which uses a high degree of parallelism. Due to higher switch throughput achieved with our cell scheduling, the cell loss probabilities and the buffer sizes necessary to guarantee a given CLR become smaller than those of other approaches based on sequential input window scheduling or output queueing     

Design of a non-blocking shared-memory copy network for ATM

The design of a copy network is presented for use in an ATM (asynchronous transfer mode) switch supporting BISDN (broadband integrated services digital network) traffic. Inherent traffic characteristics of BISDN services require ATM switches to handle bursty traffic with multicast connections. In typical ATM switch designs a copy network is used to replicate multicast cells before being forwarded to a point-to-point routeing network. In such designs, a single multicast cell enters the switch and is replicated once for each multicast connection. Each copy is forwarded to the routeing network with a unique destination address and is routed to the appropriate output port. Non-blocking copy networks permit multiple cells to be multicasted at once, up to the number of outputs of the copy network. Another critical feature of ATM switch design is the location of buffers for the temporary storage of transmitted cells. Buffering is required when multiple cells require a common switch resource for transmission. Typically, one cell is granted the resource and is transmitted while the remaining cells are buffered. Current switch designs associate discrete buffers with individual switch resources. Discrete buffering is not efficient for bursty traffic as traffic bursts can overflow individual switch buffers and result in dropped cells, while other buffers are under-used. A new non-blocking copy network is presented in this paper with a shared-memory input buffer. Blocked cells from any switch input are stored in a single shared input buffer. The copy network consists of three banyan networks and shared-memory queues. The design is scalable for large numbers of inputs due to low hardware complexity, O (N log₂ N), and distributed operation and control. It is shown in a simulation study that a switch incorporating the shared-memory copy network has increased throughput and lower buffer requirements to maintain low packet loss probability when compared to a switch with a discrete buffer copy network.     

Dynamics of TCP traffic over ATM networks

Investigates the performance of transport control protocol (TCP) connections over ATM networks without ATM-level congestion control and compares it to the performance of TCP over packet-based networks. For simulations of congested networks, the effective throughput of TCP over ATM can be quite low when cells are dropped at the congested ATM switch. The low throughput is due to wasted bandwidth as the congested link transmits cells from “corrupted” packets, i.e., packets in which at least one cell is dropped by the switch. The authors investigate two packet-discard strategies that alleviate the effects of fragmentation. Partial packet discard, in which remaining cells are discarded after one cell has been dropped from a packet, somewhat improves throughput. They introduce early packet discard, a strategy in which the switch drops whole packets prior to buffer overflow. This mechanism prevents fragmentation and restores throughput to maximal levels     

Priority mechanisms in ATM switches carrying two layer video data

Switching of two-layer coded video signals in an ATM environment is considered. To eliminate the output contention of the switch, cells from both layers are stored either in a separate or a joint buffer. The impact of these buffers on the cell loss rates and the delay variation between the two layers is investigated. An alternative buffering mechanism which enhances the switch performance is given.<>     

Performance analysis of handover delay and buffer capacity in mobile OpenFlow‐based networks

Software‐defined networking (SDN) is a network concept that brings significant benefits for the mobile cellular operators. In an SDN‐based core network, the average service time of an OpenFlow switch is highly influenced by the total capacity and type of the output buffer, which is used for temporary storage of the incoming packets. In this work, the main goal is to model the handover delay due to the exchange of OpenFlow‐related messages in mobile SDN networks. The handover delay is defined as the overall delay experienced by the mobile node within the handover procedure, when reestablishing an ongoing session from the switch in the source eNodeB to the switch in the destination eNodeB. We propose a new analytical model, and we compare two systems with different SDN switch designs that model a continuous time Markov process by using quasi‐birth–death processes: (1) single shared buffer without priority (model SFB), used for all output ports for both control and user traffic, and (2) two isolated buffers with priority (model priority finite buffering [PFB]), one for control and the other for user plane traffic, where the control traffic is always prioritized. The two proposed systems are compared in terms of total handover delay and minimal buffer capacity needed to satisfy a certain packet error ratio imposed by the link. The mathematical modeling is verified via extensive simulations. In terms of handover delay, the results show that the model PFB outperforms the model SFB, especially for networks with high number of users and high probability of packet‐in messages. As for the buffer dimensioning analysis, for lower arrival rates, low number of users, and low probability of packet‐in messages, the model SFB has the advantage of requiring a smaller buffer size.     

The UniMIN switch architecture for large-scale ATM switches

A general expansion architecture is proposed that can be used in building large-scale switches using any type of asynchronous transfer mode (ATM) switch. The proposed universal multistage interconnection network (UniMIN) switch is composed of a buffered distribution network (DN) and a column of output switch modules (OSMs), which can be any type of ATM switch. ATM cells are routed to their destination using a two-level routing strategy. The DN provides each incoming cell with a self-routing path to the destined OSM, which is the switch module containing the destination output port. Further routing to the destined output port is performed by the destination OSM. Use of the channel grouping technique yields excellent delay/throughput performance in the DN, and the virtual FIFO concept is used for implementing the output buffers of the distribution module without internal speedup. We also propose a “fair virtual FIFO” to provide fairness between input links while preserving cell sequence. The distribution network is composed of one kind of distribution module which has the same size as the OSM, regardless of the overall switch size N. This gives good modular scalability in the UniMIN switch. Performance analysis for uniform traffic and hot-spot traffic shows that a negligible delay and cell loss ratio in the DN can be achieved with a small buffer size, and that DN yields robust performance even with hot-spot traffic. In addition, a fairness property of the proposed fair virtual FIFO is shown by a simulation study     

Queuing analysis of shared‐buffer ATM switches with grouped output channels

Shared buffering and channel grouping are powerful techniques with great benefits in terms of both performance and implementation. Shared‐buffer switches are known to have better performance and better utilization than input or output queued switches. With channel grouping, a cell is routed to a group of channels instead of a specific output channel. In this way, congestion due to output contention can be minimized and the switch performance can therefore be greatly improved. Although each technique is well known by itself in the traditional study of queuing systems, their combined use in ATM networks has not been much explored previously. In this paper, we develop an analytical model for a shared‐buffer ATM switch with grouped output channels. The model is then used to study the switch performance in terms of cell loss probability, cell delay and throughput. In particular, we study the impact of the channel grouping factor on the buffer requirements. Our results show that grouping the output channels in a shared‐buffer ATM switch leads to considerable savings in buffer space. Copyright © 2001 John Wiley & Sons, Ltd.     

An efficient solution method for Markov models of ATM links withloss priorities

Algorithms for solving for the cell loss rates in an asynchronous transfer mode (ATM) network using cell loss priorities are presented. With the loss priority scheme, cells of low-priority classes are accepted only if the instantaneous buffer queue length at the cell arrival epoch is below a given threshold. The input is modeled by Markov-modulated Bernoulli processes. The effect of the loss priority scheme on data, voice, and video traffic is investigated     

Enhanced fuzzy logic‐based spray and wait routing protocol for delay tolerant networks

Delay tolerant networks are a class of ad hoc networks that enable data delivery even in the absence of end‐to‐end connectivity between nodes, which is the basic assumption for routing in ad hoc networks. Nodes in these networks work on store‐carry and forward paradigm. In addition, such networks make use of message replication as a strategy to increase the possibility of messages reaching their destination. As contact opportunities are usually of short duration, it is important to prioritize scheduling of messages. Message replication may also lead to buffer congestion. Hence, buffer management is an important issue that greatly affects the performance of routing protocols in delay tolerant networks. In this paper, Spray and Wait routing protocol, which is a popular controlled replication‐based protocol for delay tolerant networks, has been enhanced using a new fuzzy‐based buffer management strategy Enhanced Fuzzy Spray and Wait Routing, with the aim to achieve increased delivery ratio and reduced overhead ratio. It aggregates three important message properties namely number of replicas of a message, its size, and remaining time‐to‐live, using fuzzy logic to determine the message priority, which denotes its importance with respect to other messages stored in a node's buffer. It then intelligently selects messages to schedule when a contact opportunity occurs. Because determination of number of replicas of a message in the network is a difficult task, a new method for estimation of the same has been proposed. Simulation results show improved performance of enhanced fuzzy spray and wait routing in terms of delivery ratio and resource consumption. Copyright © 2014 John Wiley & Sons, Ltd.     

Omega network-based ATM switch with neural network-controlledbypass queueing and multiplexing

Multistage interconnection networks (MINs) have long been studied for use in switching networks. Since they have a unique path between source and destination and the intermediate nodes of the paths are shared, internal blocking can cause very poor throughput. This paper proposes a high throughput ATM switch consisting of an Omega network with a new form of input queues called bypass queues. We also improve the switch throughput by partitioning the Input buffers into disjoint buffer sets and multiplexing several sets of nonblocking cells within a time slot, assuming that the routing switch operates only a couple of times faster than the transmission rate. A neural network model is presented as a controller for cell scheduling and multiplexing in the switch. Our simulation results under uniform traffic show that the proposed approach achieves almost 100% of potential switch throughput     

Design and performance of Multinet switch: a multistage ATM switcharchitecture with partially shared buffers

A new ATM switch architecture is presented. Our proposed Multinet switch is a self-routing multistage switch with partially shared internal buffers capable of achieving 100% throughput under uniform traffic. Although it provides incoming ATM cells with multiple paths, the cell sequence is maintained throughout the switch fabric thus eliminating the out-of-order cell sequence problem. Cells contending for the same output addresses are buffered internally according to a partially shared queueing discipline. In a partially shared queueing scheme, buffers are partially shared to accommodate bursty traffic and to limit the performance degradation that may occur in a completely shared system where a small number of calls may hog the entire buffer space unfairly. Although the hardware complexity in terms of number of crosspoints is similar to that of input queueing switches, the Multinet switch has throughput and delay performance similar to output queueing switches     

32×32 shared buffer type ATM switch VLSIs for B-ISDNs

A set of 0.8 μm CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32×32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32×32 switching board to achieve large-scale switching systems such as 256×256 or 1024×1024 switches are discussed     

An adaptive FEC scheme for data traffic in wireless ATM networks

A new adaptive forward-error-correction scheme (AFEC) is introduced at the link layer for TCP/IP data traffic in wireless ATM networks. The fading and interference in wireless links cause high and variable error rates, as well as bursty errors. The purpose of the AFEC scheme is to provide a dynamic error-control mechanism by using Reed-Solomon coding to protect the ATM cell payload, as well as the payload type indicator/cell loss priority fields in the ATM cell header. In order to enhance the error tolerance in cell framing and correct delivery, the AFEC scheme functions within a new concept called LANET framing and addressing protection mechanisms. The AFEC scheme has been validated using a simulation testbed of a low-speed wireless ATM network     

Policing mechanism and cell loss priority control on voice cells in ATM networks using fuzzy logic

The authors present a fuzzy logic-based implementation of the policing mechanism (PM) and cell loss priority control (CLPC) functions on voice cells in asynchronous transfer mode (ATM) networks. Specifically, a redesigned model of fuzzy leaky bucket (FLB) is presented which serves as an alternative PM on the voice sources in an ATM network. As a continuation of the implementation of the FLB in the ATM network, three models of ATM switches with different algorithms are constructed, to perform CLPC on the voice cells, as well as to enhance the network throughput. Simulation results show that FLB is a better PM than the conventional leaky bucket (LB) in terms of cell loss probability and throughput while the mean transfer delay remains unchanged. It is also shown that the model of ATM switch with fuzzy token generator is the most balanced CLPC scheme as compared with the other two models.     

Deadlock Avoidance in Store-and-Forward Networks--II: Other Deadlock Types

This paper describes the construction of loop-free buffer graphs which avoid four types of buffer deadlocks in store-and-forward networks. 1) Progeny deadlock, where original messages spawnother ones, and buffer contention occurs between the original and progeny messages. This occurs when positive or negative acknowledgments are created, e.g., if messages reverse direction after encountering a path failure. 2) Copy-release deadlock, where a message copy is stored at the source node and the buffer is not released until an acknowledgment is received from the destination node. Buffer contention may arise among the original messages, stored copies, and acknowledgments. 3) Pacing deadlock, where a local flow control protocol is used between a network node and attached terminals. Buffer contention may arise between the message flows into and out of the terminal, preventing the transmission of go-ahead commands. 4) Reassembly deadlock, whereby reassembly of packetized messages at the destination node cannot be completed. The solution presented here has the novel features of not requiring preallocation of reassembly buffers before transmission of multiple packets of a multipacket message, and not requiring dedication of buffer space at intermediate nodes for individual messages. These schemes are believed to have modest buffer requirements at each node, and if adequate buffer pools are provided, will incur negligible performance degradations under normal conditions, with overhead increasing under heavy buffer usage when deadlock is near.     

Sorting-based routing algorithms of a photonic ATM cell switch:HiPower

HiPower is a photonic ATM switch having a two-layered structure, consisting of an electrical control layer and an optical transport layer, realized by a detouring hypercube interconnection network structure. Four sorting-based routing algorithms suitable for high-speed hardware control of HiPower are proposed. They are evaluated by computer simulations in terms of delay and cell loss in the switch under uniform traffic distribution. The simulation results suggest that all four methods are acceptable in their traffic characteristics and that the DD method, in which the cell nearest to its destination is given the highest priority in routing, seems to be the most attractive from the hardware implementation viewpoint. It is also confirmed that subpriority sorting based on the number of detourings reduces the delay variance. Simulation results proving that the detouring hypercube network is a practical and powerful architecture for a two-layered ATM cell switch, thus, the HiPower providing high throughput, are given     

A 622-Mb/s 8×8 ATM switch chip set with shared multibufferarchitecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8-μm BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8×8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing     

A new buffer management scheme for hierarchical shared memoryswitches

We study a multistage hierarchical asynchronous transfer mode (ATM) switch in which each switching element has its own local cell buffer memory that is shared among all its output ports. We propose a novel buffer management technique called delayed pushout that combines a pushout mechanism (for sharing memory efficiently among queues within the same switching element) and a backpressure mechanism (for sharing memory across switch stages). The backpressure component has a threshold to restrict the amount of sharing between stages. A synergy emerges when pushout, backpressure, and this threshold are all employed together. Using a computer simulation of the switch under symmetric but bursty traffic, we study delayed pushout as well as several simpler pushout and backpressure schemes under a wide range of loads. At every load level, we find that the delayed pushout scheme has a lower cell loss rate than its competitors. Finally, we show how delayed pushout can be extended to share buffer space between traffic classes with different space priorities     

An approximate analysis of shared‐buffer channel‐grouped ATM switches under imbalanced traffic

Grouping output channels in a shared‐buffer ATM switch has shown to provide great saving in buffer space and better throughput under uniform traffic. However, uniform traffic does not represent a realistic view of traffic patterns in real systems. In this paper, we extend the queuing analysis of shared‐buffer channel‐grouped (SBCG) ATM switches under imbalanced traffic, as it better represent real‐life situations. The study focuses on the impact of the grouping factor and other key switch design parameters on the performance of such switches as compared to the unichannel allocation scheme in terms of cell loss probability, throughput, mean cell delay and buffer occupancy. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is presented. Copyright © 2005 John Wiley & Sons, Ltd.     

ATM Interface Technologies for an ATM Switching System

Realization of the economical, reliable, and efficient ATM interface block becomes an important key to development of the ATM switching system when we consider new issues raised recently. In this paper, we summarize requirements for the ATM interface block and present the UNI (User Network Interface)/NNI (Network Node Interface) architecture to meet these requirements. We also evaluate the performance of the multiplexer adopting the various multiplexing schemes and service disciplines. For ATM UNI/NNI interface technologies, we have developed a new policing device using the priority encoding scheme. It can reduce the decision time for policing significantly. We have also designed a new spacer that can space out the clumped cell stream almost perfectly. This algorithm guarantees more than 99 % conformance to the negotiated peak cell rate. Finally, we propose the interface architecture for accommodation of the ABR (Available Bit Rate) transfer capability. The proposed structure that performs virtual source and virtual destination functions as well as a switch algorithm can efficiently accommodate the ABR service.