Multiple-availability-level ATM network architecture

Because of their high flexibility, ATM networks have the potential to achieve two objectives: switch cost reduction and multi-level network availability. For that purpose, this article proposes to use virtual circuit (VC) route self-healing schemes to achieve a multiple-availability-level ATM network. Flexible multi-QoS logical ATM network (Full-Net), a new concept for ATM networks, is now being studied at NTT Laboratories. Full-Net is a very flexible network design strategy for survivable networks that is based on a self-healing VC network. Defining several logical configurations of the VC network allows us to support multiple levels of network availability, simplifies the adaptation to future and unknown service requirements, and significantly reduces overall ATM network cost. Offering different levels of availability not only saves the network's resources, but also allows the network operator to provide its customers with services at the most appropriate cost. We introduce the advantages of VC route restoration for ATM networks, and compare virtual path (VP) level and physical level restoration strategies. We explain Full-Net's concept, propose a VC route self-healing scheme, and show the impact of the logical network configurations on network survivability and resource management     

Design of a generalized priority queue manager for ATM switches

Meeting quality of service (QoS) requirements for various services in ATM networks has been very challenging to network designers. Various control techniques at either the call or cell level have been proposed. In this paper, we deal with cell transmission scheduling and discarding at the output buffers of an ATM switch. We propose a generalized priority queue manager (GPQM) that uses per-virtual-connection queueing to support multiple QoS requirements and achieve fairness in both cell transmission and discarding. It achieves the ultimate goal of guaranteeing the QoS requirement for each connection. The GPQM adopts the earliest due date (EDD) and self-clocked fair queueing (SCFQ) schemes for scheduling cell transmission and a new self-calibrating pushout (SCP) scheme for discarding cells. The GPQM's performance in cell loss rate and delay is presented. An implementation architecture for the GPQM is also proposed, which is facilitated by a new VLSI chip called the priority content-addressable memory (PCAM) chip     

Evolutionary architecture for an all-services ATM access network

This paper presents a flexible concept for a broadband subscriber access network which minimizes investment costs by predominantly using the existing network infrastructure. The target network may consist of either a coaxial tree-and-branch structure or symmetrical copper pairs to the subscriber, and is connected to the central head station with the aid of optical feeder lines which can be implemented or enhanced by a passive optical network (PON). In the event of an increase in bit rate requirements, the coaxial network can be expanded by dividing it into smaller, optically fed subnetworks or by supplementing it with optical overlay systems. Flexibility, expandability and low costs are achieved through the standard ATM format implemented for the signals of all interactive services down to the network termination units on the subscriber side. Those signals are transmitted in the coaxial network in frequency bands above the CATV band in accordance with a multiple of the CATV channel width to ensure that the modulation and demodulation is implemented in a cost-efficient manner while providing ‘bit rate on demand’ for a suitably high number of subscribers. Separation of the network termination unit from the customer premises equipment enables a flexible, cost-efficient subscriber configuration to be selected, existing domestic wiring to be used and several completely different subscriber terminals to be simultaneously connected.     

临近空间光传输网络结构设计

利用高性能激光链路互联临近空间平台,组建临近空间平台光网络,向上可与卫星互联,向下可与地面站互联,能够实现高速、大容量及远程数据中继。从构建临近空间光传输网络结构出发,首先根据平台之间连接方式的不同,列举出四种可能存在的HAP网络拓扑结构;然后从云层高度、大气效应、微波接入需求和临近空间环境四个方面总结了影响HAP网络结构设计的因素;最后参考以上分析结果,对波长资源受限的多平台网络拓扑进行分析。     

A new priority control of ATM output buffer

A new ATM output buffer management strategy with priority control function is proposed, based on four types of cell classes. This strategy can use system resource more effectively, meet the quality of service (QOS) requirements (i.e. cell loss probabilities and delay characteristics) of different services, and also can reduce the complexity of buffer. Furthermore, overload from lower priority traffic doesn't degrade the performance of higher priority traffic (i.e. cell loss rate and cell delay characteristics).     

Medium access control priority mechanism for a DQMAN-based wireless network

The analysis of an access priority mechanism for a high-performance Medium Access Control (MAC) protocol, the Distributed Queueing MAC protocol for wireless Ad Hoc Networks (DQMAN), is presented in this letter. DQMAN is comprised of a hierarchical, dynamic, and spontaneous masterslave clustering algorithm together with an embedded treesplitting collision resolution algorithm based on access minislots. The responsibility of being master entails extra functionality, and thus extra energy consumption. Therefore, this responsibility must be shared in a dynamic manner among all the stations of the network in order to ensure fairness in the system. By allowing those stations acting as master stations to avoid contention to get access to the channel, their average packet transmission delay can be effectively reduced compared to that of slave stations. Consequently, stations may be encouraged to operate in master mode regardless of the extra functions they may have to carry out. We analyze in this letter the reduced average packet transmission delay for masters.     

Design of a non-blocking shared-memory copy network for ATM

The design of a copy network is presented for use in an ATM (asynchronous transfer mode) switch supporting BISDN (broadband integrated services digital network) traffic. Inherent traffic characteristics of BISDN services require ATM switches to handle bursty traffic with multicast connections. In typical ATM switch designs a copy network is used to replicate multicast cells before being forwarded to a point-to-point routeing network. In such designs, a single multicast cell enters the switch and is replicated once for each multicast connection. Each copy is forwarded to the routeing network with a unique destination address and is routed to the appropriate output port. Non-blocking copy networks permit multiple cells to be multicasted at once, up to the number of outputs of the copy network. Another critical feature of ATM switch design is the location of buffers for the temporary storage of transmitted cells. Buffering is required when multiple cells require a common switch resource for transmission. Typically, one cell is granted the resource and is transmitted while the remaining cells are buffered. Current switch designs associate discrete buffers with individual switch resources. Discrete buffering is not efficient for bursty traffic as traffic bursts can overflow individual switch buffers and result in dropped cells, while other buffers are under-used. A new non-blocking copy network is presented in this paper with a shared-memory input buffer. Blocked cells from any switch input are stored in a single shared input buffer. The copy network consists of three banyan networks and shared-memory queues. The design is scalable for large numbers of inputs due to low hardware complexity, O (N log₂ N), and distributed operation and control. It is shown in a simulation study that a switch incorporating the shared-memory copy network has increased throughput and lower buffer requirements to maintain low packet loss probability when compared to a switch with a discrete buffer copy network.     

Hardware-software architecture of the SWAN Wireless ATM network

The SWAN (Seamless Wireless ATM Network) system provides end-to-end ATM connectivity to mobile end-points equipped with RF transceivers for wireless access. Users carrying laptops and multimedia terminals can seamlessly access multimedia data over a backbone wired network while roaming among room-sized cells that are equipped with basestations. The research focus on how to make ATM mobile and wireless distinguishes SWAN from present day mobile-IP based wireless LANs. This paper describes the design and implementation of the ATM-based wireless last-hop, the primary components of which are the air-interface control, the medium access control, and the low-level ATM transport and signalling.The design is made interesting by its interplay with ATM; in particular, by the need to meaningfully extend over the wireless last-hop the service quality guarantees made by the higher level ATM layers. The implementation, on the other hand, is an example of hardware-software co-design and partitioning. A key component of the wireless hop implementation is a custom designed reconfigurable wireless adapter card called FAWN (Flexible Adapter for Wireless Networking) which is used at the mobiles as well as at the basestations. The functionality is partitioned three-way amongst dedicated reconfigurable hardware on FAWN, embedded firmware on FAWN, and device driver software on a host processor. Using an off-the-shelf 625 Kbps per channel radio, several of which can be supported by a single FAWN adapter to provide multiple channels, per-channel unidirectional TCP data throughput of 227 Kbps (or, 454 Kbps bidirectional) and per-channel unidirectional native ATM data throughput of 210 Kbps (or, 420 Kbps bidirectional) have been obtained.     

A novel architecture for queue management in the ATM network

The author presents four architecture designs for queue management in asynchronous transfer mode (ATM) networks and compares their implementation feasibility and hardware complexity. The author introduces the concept of assigning a departure sequence number to every cell in the queue so that the effect of long-burst traffic on other cells is avoided. A novel architecture to implement the queue management is proposed. It applies the concepts of fully distributed and highly parallel processing to schedule the cells' sending or discarding sequence. To support the architecture, a VLSI chip (called Sequencer), which contains about 150 K CMOS transistors, has been designed in a regular structure such that the queue size and the number of priority levels can grow flexibly     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

Broad-band ATM network architecture based on virtual paths

Broadband transport techniques and network architectures based on the virtual path concept are examined. ATM (asynchronous transfer mode) techniques, when coupled with recent technological innovations, are expected to pave the way for future universal transport networks. The virtual path concept, which exploits the ATM's capabilities, is proposed to construct an efficient and economic network. The concept matches current and anticipated technological trends well. Characteristics and implementation techniques of virtual paths are discussed. Advantages of the virtual path concept and its impact on the transport network architecture are demonstrated. The virtual path strategy is also shown to provide efficiently for networks with dynamic reconfiguration capability which will enhance network performance. Some basic analytical results on the dynamic control effects of virtual paths are provided     

Analysis of a priority cell discarding method for ATM networks

One of the most important problems that must be solved in ATM networks is the priority cell discarding (PCD). A two priorities cell discarding method is suggested and analyzed under conditions of discrete time cell arrival. By introducing the operator, an iterative algorithm that can accelerate the speed of convergence when calculating the cell loss probability is suggested. The effectiveness of the PCD in ATM networks is proved by the numeric results.This work was supported in part by the National Key Laboratory of ISN.     

Voice over ATM: an evaluation of network architecture alternatives

This article describes eight application scenarios in which there is a business case for voice over ATM. It then evaluates alternative network architectures for implementing the required network functionality. The article incorporates much of the ongoing work of the ATM Forum and the ITU, but does not restrict itself to standards and implementation agreements. In addition, it evaluates nonstandardized alternatives for ATM transport of voice traffic. There are two main areas: N×64 kb/s structured data transfer, also known as composite cell transport-a network operator may aggregate individual voice calls into N×64 kb/s blocks for transport to an intermediate point in the network. At that point the individual calls need to be remapped into new M×64 kb/s blocks for the next stage of their transport. Architectural alternatives and advantages of remapping are investigated. Interworking of signalling is of two types: network interworking, in which the end users are connected to non-ATM networks and an ATM network is used for backbone transport; and service interworking, in which an ATM user is connected to a non-ATM user. Functionality and architectural alternatives for network and service interworking are evaluated     

一种新的集成自愈技术及其算法

本文首先提出了容量平衡优化（ＣＥＰ）、共享自愈环（ＳＳＲ）和分布式动态自愈网（ＤＳＨ）三者集成的自愈技术,提出了基于最短路由业务量阵（ＳＲＭＴ）的ＳＳＲ空闲容量分配算法,而对于ＤＳＨ,从端到端重选路由和网络资源利用率的观点看,基于通道恢复技术比基于链路恢复技术更有效,本文提出了基于通道恢复的集成自愈设计技术及其算法。数值结果表明：本文提出的集成自愈技术及其算法可有效地节约容量需求。     

一种基于CORBA和TMN结构的ATM网络管理模型

本文给出了一种基于CORBA和TMN结构的ATM网络管理模型。首先介绍模型的OS结构,并将ATM与其传输网SDH进行集成管理;其次定义了该模型在不同域之间交换信息的接口,即所谓的Xcoop。结果表明该模型能够实现分布式网络管理、保证宽带连接业务的端到端QoS,并且有故障管理和配置管理功能。     

Design and performance evaluation of a banyan network basedinterconnection structure for ATM switches

This paper presents a new self-routing packet network called the plane interconnected parallel network (PIPN). In the proposed design, the traffic arriving at the network is shaped and routed through two banyan network based interconnected planes. The interconnections between the planes distribute the incoming load more homogeneously over the network. The throughput of the network under uniform and heterogeneous traffic requirements is studied analytically and by simulation. The results are compared with the results of the baseline network and another banyan network based parallel interconnection network. It is shown that, for the proposed design, a higher degree of heterogeneity results in better performance     

Design implementation of ATM switch with input priority anddistributed output buffers

A switch architecture for ATM is described which uses a simple priority module to resolve input contention and a distributed design to permit transfer of input cells to the first free output buffer. The switch has been synthesised using VHDL software and a target generic library and can operate at speeds >400 Mbit/s     

Design of fault-tolerant ATM switch based on parallel architecture

A fault-tolerant ATM switch comprising a distribution network and several routing networks in parallel is proposed. As the distribution network carries out part of the routing process, the routing networks are truncated, giving low overall complexity. A performance evaluation of the switch is presented. The switch outperforms replicated networks but requires lower complexity     

新一代校园网络架构的仿真与优化研究

信息技术日新月异,随着高校校园网出现的技术与设备老化、网络性能日益下降以及其运行过程中受到新网络安全问题不断威胁的现象,升级改造成高效、稳定、快捷的新一代校园网络架构已势在必行。要对校园网络进行整体改造,需要投入巨大的资金,所以在改造之前应该利用各种手段进行调研和分析。网络仿真技术可以对新协议进行初步实现和验证,并有利于及时调整和改进。结合网络技术和硬件产品,利用GNS3网络仿真软件对真实校园网环境进行全网仿真还原,并通过对仿真网络的测试、分析,提出新一代校园网络架构的配置优化、架构优化和安全优化的方案。