Vibration reliability characterization of PBGA assemblies

Generally, the low-cycle fatigue induced by thermal cycling is the major concern in the reliability of surface mount technology for electronic packaging, but the high-cycle fatigue induced by vibration can also contribute significant effect, especially for applications in automobile, military, and avionic industries. To assess vibration induced fatigue failures, the dynamic properties of printed circuit board (PCB) assemblies play a very important role. In this paper, the dynamic properties of a plastic ball grid array (PBGA) assembly were characterized by using experimental modal testing and finite element analysis. The bare PCB and PCB assembly with PBGA modules mounted were tested and analyzed separately, so that the influence of PBGA modules on the PCB’s dynamic properties could be identified. It was found that mounting PBGA modules to PCB increased the stiffness of the PCB. Results of constant-amplitude vibration reliability testing of the PBGA assembly are also reported. It was found that the PBGA assembly was vulnerable to vibration, and fatigue failure always occurred at the corner solder balls of the PBGA module.     

Methodology for predicting solder joint reliability in semiconductor packages

A new experimental method for detecting solder joint strain in package assemblies using digital image correlation metrology has been developed. A new methodology is proposed which utilizes strain data generated by this technique for predicting solder joint fatigue life for any desired package configuration based on a reference configuration. This approach has significant practical appeal since it obviates brute-force temperature cycle testing for the qualification of every new variation of an existing package configuration. In this paper, we describe the principle, experimental set-up and sample preparation techniques for this method. We present typical strain data on solder joints for a ball grid array (BGA) package mounted to a FR4 PC board. We apply the technique to the prediction of temperature cycling reliability of a Ceramic BGA package wherein, the effect of a new substrate material is examined and the predictions are confirmed based on empirical temperature cycle testing data. Finally, we show a co-relation of measured strain data with computations by finite element modeling performed for a specific package configuration.     

Simulating package behavior under power dissipation using uniformthermal loading

The thermomechanical behavior of electronic packages under power dissipation is simulated using uniform thermal loading. Two packages are studied, a large periphery leaded plastic quad flat pack (PQFP) package and a more compact plastic ball grid array (PBCA) package, both mounted on a printed circuit board (PCB). Experimentally verified linear elastic finite element models are used to find the displacements at the predicted failure location during power dissipation, and then during uniform thermal loading. The results for the two cases are then analyzed to find correlations between power dissipation levels and equivalent heating temperatures. One use of the results could be to replace power cycling fatigue tests with thermal cycling tests, For the packages studied, the results revealed that very little uniform heating is required to simulate the thermomechanical effects at the failure location resulting from power dissipation. Due to the prestrained state of the packages at room temperature, power dissipation decreases the expansion mismatch while increasing the thermal mismatch between package and PCB     

Finite element simulation of thermal fatigue in multilayer structures: thermal and mechanical approach

The large difference in thermal expansion between dissimilar materials present in any electronic package is the source of a major problem to be solved in order to achieve improved reliability. In this paper, simplified thermal and mechanical finite element models are presented for the analysis of thermal stress derived problems. The problems investigated here include, thermal stresses in adhesive backbonds in surface mounted structures and effects of thermal fatigue in soft solder interfaces in conventional power modules such as insulated gate bipolar transistors modules. Full multi-dimensional mechanical and thermal analysis is made by using the commercial engineering computer package . Validation of the thermal simulation is achieved by comparison between simulation and experimental test results, whereas a simple analytical model based upon the lap joint theory is used to verify the structural simulation.     

Impact of FEM simulation on reliability improvement of packaging

An important role of packages is the protection of the chip to environmental influences like moisture, pollutants and other chemical active species. If the chip is exposed these influences for instance corrosion is resulting and it may come to early failures.The reliability of the package is affected by thermo-mechanical stress. Due to this, an essential aspect of the package design is the careful combination of materials to avoid mechanical stress and to improve the thermal resistance of the package, which is significant for example in power or automotive applications. For a reduction of the mechanical stress, a good heat conductivity into the ambient and by this a small thermal resistance of the package should be aspired.Finite element analysis. (FEM) can give a fast and reliable solution to investigate the influence of mechanical stress as well as the thermal behaviour of the package, depending on the material properties and on the package geometry. For the finite element analysis special boundary conditions like convection and radiation and the influence of the board have to be taken into account.     

Computational parametric analyzes on the solder joint reliability of bottom leaded plastic (BLP) package

The bottom-leaded plastic (BLP) package is a lead-on-chip type of chip scale package (CSP) developed mainly for memory devices. Because the BLP package is one of the smallest plastic packages available, solder joint reliability becomes a critical issue. In this study, a 28-pin BLP package is modeled to investigate the effects of molding compound and leadframe material properties, the thickness of printed circuit board (PCB), the shape of solder joint and the solder pad size on the board level solder joint reliability. A viscoplastic constitutive relation is adopted for the modeling of solder in order to account for its time and temperature dependence on thermal cycling. A three-dimensional nonlinear finite element analysis based on the above constitutive relation is conducted to model the response of a BLP assembly subjected to thermal cycling. The fatigue life of the solder joint is estimated by the modified Coffin-Manson equation. The two coefficients in the modified Coffin-Manson equation are also determined. Parametric studies are performed to investigate the dependence of solder joint fatigue life on various design factors.     

PBGA封装热可靠性分析

对PBGA封装体建立了有限元数值模拟分析模型。模型采用无铅焊点,完全焊点阵列形式。研究了封装体在经历IPC9701标准下的五种不同温度循环加载后,受到的热应力、应变,以及可能的失效形式。结果表明,焊点是封装体结构失效的关键环节,焊点所受应力大小与焊点位置有关。比较了不同温度循环下封装体的疲劳寿命。其结果为提高封装体的可靠性和优化设计提供了理论依据。     

Measurement and Simulation of Stacked Die Thermal Resistances

Packages with multiple dies provide additional challenges when documenting their thermal performance. One style of multiple dies packages stacks the die on top of each other with a die attach adhesive. This paper explores the thermal performance of such packages in a wire bond plastic ball grid array package with three different die configurations. The thermal performance of the package was determined using the JEDEC JESD51 specifications. Since there were three different effective die sizes, the data allowed a better validation of the finite element thermal simulation techniques than can be obtained with only a single die size. Die size is usually the most important predictor of plastic ball grid array thermal performance. In this case, packages built with the same materials and substrate had a Theta-JA (2s2p board, natural convection) that differed by 100% as a result of a change in effective die size. With a validated simulation method, additional power distributions were simulated and compared to results obtained by superposition techniques.      

Warpage studies of HDI test vehicles during various thermalprofilings

New techniques and technologies involved in the miniaturization of printed wiring board (PWB) fabrication are rapidly emerging. The quality, performance, and reliability of surface mount assemblies built on these next-generation boards will depend on many factors, including thermally induced warpage. Therefore, quantitative warpage measurement is critical in new PWB assembly design evaluation, and determining overall thermal performance characteristics. Using an automated infrared reflow oven simulation system, the warpage of six bare high density interconnect (HDI) samples is measured under two different heating profiles. Out-of-plane surface displacement is measured with a noncontact shadow Moire technique and resolution enhancement method called phase-stepping. The two types of samples evaluated were built for the purpose of warpage study, where physical data could be used to validate finite element analysis (FEA) results. The warpage results obtained with the two thermal profiles will be presented     

Design and Fabrication of a Flip-Chip-on-Chip 3-D Packaging Structure With a Through-Silicon Via for Underfill Dispensing

This paper presents a new package design for multichip modules. The developed package has a flip-chip-on-chip structure. Four chips [simulating dynamic random access memory (DRAM) chips for demonstration purpose] are assembled on a silicon chip carrier with eutectic solder joints. The I/Os of the four chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. A through-silicon via (TSV) hole is made at the center of the silicon chip carrier for optional underfill dispensing. The whole multichip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly and X-ray inspection, the underfill process is applied to some selected specimens for comparative study purpose. The underfill material is dispensed through the center TSV hole on the silicon chip carrier to encapsulate the solder joints and the four smaller chips. Subsequently, scanning acoustic microscopy (SAM) is performed to inspect the quality of underfill. After the board-level assembly, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of all specimens is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1200 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, instead of solder joints. The features and merits of the present package design are discussed in details in this paper.     

Nonuniform temperature and strain fields in a powered package

This paper analyzes the nonuniform temperature and strain fields resulting from power dissipation in an electronic package. A 208 lead plastic quad flat pack (PQFP) manufactured by Texas Instruments is used to show the temperature distribution and mechanical deformation resulting from power dissipation in the package. The package is tested experimentally and thermally modeled using finite element analysis to obtain the temperature distribution in the active package. The moire interferometry technique is used to acquire displacement contours of an active PQFP and the results are compared to a uniformly heated sample. The results revealed that the thermal loading due to internal power dissipation produces significantly different strains than a uniformly heated sample     

Application of the Taguchi method to chip scale package (CSP)design

A three-dimensional (3-D) nonlinear finite element model of an overmolded chip scale package (CSP) on flex-tape carrier has been developed by using ANSYS^TM finite element simulation code. The model has been used to optimize the package for robust design and to determine design rules to keep package warpage within acceptable Joint Electron Device Engineering Council (JEDEC) limits. An L₁₈ Taguchi matrix has been developed to investigate the effect of die thickness and die size, mold compound material and thickness, flex-tape thickness, die attach epoxy and copper trace thicknesses, and solder bail collapsed stand-off height on the reliability of the package during temperature cycling. For package failures, simulations performed represent temperature cycling 125°C to -40°C. This condition is approximated by cooling the package which is mounted on a multilayer printed circuit board (PCB) from 125°C to -40°C. For solder ball coplanarity analysis, simulations have been performed without the PCB and the lowest temperature of the cycle is changed to 25°C. Predicted results indicate that for an optimum design, that is low stress in the package and low package warpage, the package should have smaller die with thicker overmold. In addition to the optimization analysis, plastic strain distribution on each solder ball has been determined to predict the location of solder ball with the highest strain level. The results indicate that the highest strain levels are attained in solder balls located at the edge of the die. The strain levels could then be used to predict the fatigue life of individual solder balls     

Fatigue life evaluation of wire bonds in LED packages using numerical analysis

Reliability of LED packages is evaluated using several tests. When a thermal shock test, which is one of the reliability tests, is conducted, the most common failure mode is wire neck breakage. In order to evaluate the wire bonding reliability of LED packages, performing the thermal shock test is time-consuming. In this paper the wire bonding reliability for LED packages is evaluated by using numerical analysis. A wire bonding lifetime model for the thermal shock test was developed, which is based on Coffin-Manson fatigue law. The model was calibrated from fatigue data of thermal shock tests and volume averaging accumulated plastic strains. The accumulated plastic strains were calculated by using finite element analysis corresponding to the test conditions. The test conditions were changed by silicones, package sizes, wire bonding diameters, heights, and lengths. The calibrated model was used to estimate the number cycle to failure so that the wire bonding reliability for the thermal shock test was evaluated by performing the numerical analysis. Furthermore, we used a response surface methodology to study the relationship between the wire loop and the accumulated plastic strain to determine the optimal wire loop. The plastic strain was a function of diameter, height and length. At the optimal point, the number of cycle to failure for the thermal shock test was suggested using the wire bonding lifetime model.     

Thermal design of a broadband communication system with detailed modeling of TBGA packages

This paper presents a thermal modeling of a broadband network communication box partitioned into two stacked modules. A printed circuit board (PCB) is inside each module where an array of 16 tape ball grid array (TBGA) packages is surface mounted to the PCB. The TBGA package dissipates 6 W power each. In addition, 12 W of power is dissipated from four plastic ball grid array (PBGA) packages on the PCB. Pin-fin heat sinks are attached to the TBGA packages using silica-filled epoxy to enhance heat dissipation. Pin-fin heat sinks are also attached to the PBGA packages. Two exhaust fans are mounted at the flow exit to draw ambient air into the system at approximately 200 linear feet per minute (LFM) of velocity. The full Navier–Stokes equations for airflow are solved to simulate the forced convection cooling in the electronic module. Buoyancy effect was considered in the numerical model by incorporating Boussinesq-approximation. The TBGA packages are modeled in detail in order to obtain the package junction temperatures for system reliability evaluation and thermal design optimization. Detailed models of the attached pin-fin heat sinks and the epoxy interfaces are also utilized in this study. Compact heat sink model composed of a base plate and a resistance fluid volume is applied to model heat dissipation from the heat sinks attached to the four PBGA packages. System fan curve is used to simulate the fan operating conditions. The effect of changing system thermal design on the TBGA package junction temperatures as well as the hydraulic operating conditions of the system fans are examined and reported herein. The effect of radiation heat transfer is also examined. The importance of detailed modeling of the high power TBGA packages is demonstrated in this study. Simulation results were compared with JEDEC thermal test data under similar conditions of airflow.     

QFN封装元件组装工艺技术的研究

QFN(Quad Flat No-lead Package,方形扁平无引脚封装)是一种焊盘尺寸小、体积小、 以塑料作为密封材料的新兴表面贴装芯片封装技术。由于底部中央大暴露焊盘被焊接到PCB的散热焊 盘上,这使得QFN具有极佳的电和热性能。QFN封装尺寸较小,有许多专门的焊接注意事项。文章 介绍了QFN的特点、分类、工艺要点和返修。     

Solder-joint reliability of HVQFN-packages subjected to thermal cycling

In this work experimental results of thermal cycling tests on HVQFN-packages mounted on printed circuit boards are combined with finite element analyses. Validating the finite element analyses by a selected series of small, medium and large HVQFN-packages assembled on printed circuit boards, allows us to determine the performance of this family. To be able to do that, the discriminating parameters that determine the board level performance of this family need to be understood. The emphasis is on the fatigue life of the soldered interconnections as it is influenced by the thermal stress load, the board thickness, and the dimension of the package. Data from different experimental set-ups are compared. An important parameter in this respect is the inclusion of the base material of the panels. The test loads were set to cycling at −40 °C/+125 °C and −20 °C/+100 °C. The results prove that the essential physical properties governing the fatigue life are the stiffness of the complete assembly and the thermal expansion mismatch between the parts.     

高密度高可靠CQFN封装设计

文中阐述了高速、高性能集成电路所需高密度、高可靠的表面贴装型陶瓷封装,讨论了多层高温共烧陶瓷工艺如何设计与塑料封装QFN完全兼容。结合0.50 mm节距CQFN72外壳设计,就如何解决CQFN封装的散热、高频电性能、薄型封装的气密性和结构强度,以及封装电路的二次组装中助焊剂清洗不彻底、焊接层/焊点有空洞和桥连短路、焊点难检查和返工困难等问题进行了论述,为高密度、高性能、高可靠封装提供了新的封装结构和技术途径。     

Spacing optimization of high power LED arrays for solid state lighting

This paper provides an analytical approach to determine the optimum pitch by utilizing a thermal resistance network,under the assumption of constant luminous efficiency.This work allows an LED array design which is mounted on a printed circuit board(PCB) attached with a heat sink subject to the natural convection cooling. Being validated by finite element(FE) models,the current approach can be shown as an effective method for the determination of optimal component spacing in an LED array assembly for SSL.     

Spacing optimization of high power LED arrays for solid state lighting

This paper provides an analytical approach to determine the optimum pitch by utilizing a thermal resistance network, under the assumption of constant luminous efficiency. This work allows an LED array design which is mounted on a printed circuit board (PCB) attached with a heat sink subject to the natural convection cooling. Being validated by finite element (FE) models, the current approach can be shown as an effective method for the determination of optimal component spacing in an LED array assembly for SSL.     

The accuracy of structural approximations employed in analysis ofarea array packages

At the present time, area-array packages are a very common electronics packaging approach. One of the major concerns in designing such packages is the reliability of solder joints, die, and the various material interfaces present in the package. Currently, analytical, numerical, and experimental methods are employed in the analysis of thermo-mechanical stresses/strains in area array packages. The sources of error in these analytical and numerical models may be broadly characterized as being due to geometry representation, material behavior, solution procedure, and due to the accuracy in representing the load history. In this paper we assess the errors in package models due to geometry representation and material behavior using a representative area-array package, namely the 225 input/output (I/O) plastic ball grid array (PBGA). The package deformation due to a fixed temperature change is experimentally characterized using Moire interferometry and numerically simulated using both two- and three-dimensional finite element models. The difference in behavior between the finite element prediction and experimental results is explained using solder material behavior data available in the literature. A comparison of accuracy as well as efficiency is made between the different finite element models. Finally, conclusions are drawn on the aspects of package construction and material that influence behavior, and on the most efficient finite element model to accurately capture this behavior