基于BP神经网络的大规模电路模块级故障快速诊断方法

根据大规模电路故障诊断网络撕裂法和交叉撕裂搜索方法,采用基于误差反向传播算法的多层前向神经网络(BP神经网络)记载多次撕裂信息,提出了一种新型基于BP神经网络的大规模电路模块级快速诊断方法。该方法能快速有效地并行处理定位故障模块,具有测前工作量小,实时诊断性强等优点。     

Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.     

A novel high-throughput method for table look-up based analog design automation

Analog circuit synthesis ofen requires repeated evaluations of circuit under design to reach the final design goals. Circuit simulations using SPICE can provide accurate assessment of circuit performance. Spice simulations are costly and incur significant overhead. A faster transistor-level evaluation is needed to provide higher throughput for synthesis applications. Further, miniaturization of FET’s has added physical effects into SPICE models, which complicated their equations with every generation. That complication has forced analog synthesis tool developers and circuit designers alike to perform circuit evaluations using SPICE.Analog circuit design tools largely failed in their declared goal, to take over circuit optimization tasks from human designers mainly due to over simplications using custom-developed equations for evaluating circuit performance. Since it is more and more difficult to accurately capture transistor behavior with each new generation of silicon technology, a more practical approach to analog design automation is to keep human engineers at the center of the design flow by providing them with as much needed decision-supporting data as quickly as possible. Mapping the trade-off landscape of a topology with respect to design specifications, for example, can save designers trial and error time. This approach to analog design automation requires less accuracy from the simulation sign-off tools, such as SPICE. However, it demands much faster response for circuit performance evaluations with sufficient accuracy.In this paper, a new solution to both calculation overheads and model complexity is proposed. The proposed fast evaluation method uses a novel look-up table (LUT) algorithm to extract circuit information from complex physics-based transistor models used by SPICE. The model makes use of contemporary memory space, by replacing equations with look-up tables in addition to advanced interpolation methods. The achieved improvement is over 100× throughput and complete decoupling from physical phenomena compared to SPICE run-time, in exchange for few gigabytes of data per device. Examples are shown for the effectiveness of replacing SPICE with our model in a transistor sizing flow, while keeping 99% of the samples inside the 5% error range on 180 nm and 40 nm CMOS processes. The proposed solution is not intended to replace sign-off quality tools, such as SPICE. Rather, it is intended to be used as a fast performance evaluator in analog design automation flows.     

Automated topology synthesis of analog and RF integrated circuits: A survey

The puzzle of automatically synthesizing analog and radio frequency (RF) circuit topology has not yet been offered with an industrially-acceptable solution although endeavors still continue to seek a conquest in this area. This survey provides a comprehensive study of the techniques utilized for this purpose. The existing methods are analyzed from four different viewpoints, namely, structural view, conceptual view, implementation view, and application view. Different schemes are perused with their advantages and drawbacks discussed in the context of balanced performance between configuration-space coverage and search efficiency. Some prospective trends are pointed out to shed light on the upcoming research activities.     

Energy-aware routing in sensor networks: A large system approach

In many sensor networking environments, the sensor nodes have limited battery capacity and processing power. Hence, it is imperative to develop solutions that are energy-efficient and computationally simple. In this work, we present a simple static multi-path routing approach that is optimal in the large-system limit. In a network with energy replenishment, the largeness comes into play because the energy claimed by each packet is small compared to the battery capacity. This static routing scheme exploits the knowledge of the traffic patterns and energy replenishment statistics, but does not need to collect instantaneous information on node energy. We also develop a distributed solution of the optimal policy, as well as heuristics to build the set of pre-computed paths. The simulations verify that the static scheme outperforms leading dynamic routing algorithms in the literature, and is close to the optimal solution when the energy claimed by each packet is relatively small compared to the battery capacity.     

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout.     

A novel test compression algorithm for analog circuits to decrease production costs

Minimizing the manufacturing test time for ICs is one of the main keys to reducing the product cost. We introduce a methodology for automated test compression for electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find the minimum for these computationally hard integrals, which corresponds to the optimally compressed analog test. We demonstrate with an op-amp, VCO, and CMOS inverter that the method consistently reduces the length of each test by an average of 93%. Our technology can compress tests in the presence of process variation and utilize parallel processing to speed up the compression algorithm.     

大规模模拟电路故障诊断方法研究

测前工作量大和故障定位过程复杂等问题,使传统的大规模模拟电路故障诊断方法研究不再适应当前的社会发展需求,因此构建高效全面的新型故障诊断方法就变得尤为重要。本文通过对撕裂法和BP网络改进算法等新兴方法进行深入的研究,来得出其具体应用和实施的可能性。     

Synthesis method for testable electrical networks using 1st order building blocks

This work presents a method for synthesizing testable continuous-time linear time-invariant electrical networks using 1st order blocks for the implementation of analog linear circuits. A functional-structural fault model for the block, and a fault dictionary are proposed together with a simple set of test vectors. The method allows, also, the fault grade evaluation for the modeled faults. The results obtained from the two application examples have shown the suitability of the approach as a design for test method for analog circuits.     

Design of a window comparator with adaptive error threshold for online testing applications

This paper presents a novel window comparator circuit whose error threshold adjusts adaptively with respect to its input signal levels. Advantages of adaptive error thresholds over constant or relative error thresholds in analog testing applications are discussed. Analytical equations for guiding the design of the comparator circuitry are derived. The proposed comparator circuit has been designed and fabricated using a CMOS technology. Measurement results of the fabricated chip are presented.     

A high-precision current-mode multifunction analog cell suitable for computational signal processing

In this paper, a high linear, low-voltage two-quadrant current squarer as multifunction analog cell, is presented. To implement the squarer circuit, translinear loops with matched NMOS transistors operating in weak inversion region are used. The proposed cell is used as a basic building block for current-mode computational analog functions such as rectifier (absolute-value), multi-input vector summation and exponential function generator. We perform post-layout plus Monte Carlo simulations of the presented functions with 0.18 μm (level-49 parameters) TSMC CMOS technology that prove their superiority over some other advanced works and robustness against PVT (process, voltage and temperature) variations.     

利用DMM比例测量法检定电阻箱程序设计

本文就传统检定电阻箱方法中存在测量误差较大、操作繁琐、效率低的问题,在介绍了DMM比例测量功能概念,比例法检定电阻箱原理、接线方法和优点的同时,提出了利用DMM比例测量功能实现检定电阻箱的方法,并描述了在LabVIEW 2011开发环境下设计检定电阻箱程序。该方法充分利用了DMM已有的测量和程控功能,除具有操作更简便,效率高和测量误差较小外,更具有易于推广应用和普及前景,对从事计量检定、自动化测量工作者具有很高的参考借鉴价值。     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

一种用于APFC的模拟乘法器设计

在有源功率因数校正技术(APFC)中,通过对乘法器的输出与电感电流的峰值比较,控制功率开关管的开启与关断,使输入电流峰值包络跟随输入电压,功率因数理论上为单位值。而提高乘法器的线性度,减小非线性误差成为研究模拟乘法器的一个重要方向。本文提出的模拟乘法器采用有源衰减器显著的增大了输入信号电压范围,更重要的是在有源衰减电路中引入负反馈有效的减小了乘法器的非线性误差。基于CSMC 0.5um BCD工艺,采用Hspice进行仿真验证,在电源电压5V条件下,乘法器的一输入端的输入范围为0~2V,非线性误差小于0.6%,另一输入端的输入范围为1~4V,非线性误差小于0.3%。总谐波失真小于1.8%。     

Fuzzy optimization models for analog test decisions

Test decisions still constitute one of the most difficult and time-consuming design tasks. This is particularly true in the analog domain where some basic test questions have not yet been completely resolved. Since the gap between a good and a bad analog circuit is not always well-defined, extensive tests may result in the rejection of many fault-free ICs. The objective of this article is to propose fuzzy optimization models that can help in the more realistic formulation and resolution of the analog test problem. The set of good or fault-free ICs is considered as a fuzzy set. Each performance test is represented by a membership function. A global test measure is obtained by aggregating all the performance tests. An illustrative example using these concepts is provided.     

适用于模数统一测试的故障隔离方法

介绍了一种实用的故障隔离方法及其实现。该方法既适用于模拟电路又适用于数字电路的故障隔离，已成功用于模数混合电路单元故障诊断系统。     

Current testing in dynamic CMOS circuits

Current testing of dynamic CMOS integrated circuits with single phase clock is investigated. The analysis is performed on a single phase stage dynamic module in the presence of internal bridging defects of low resistance. These defects produce intermediate voltage levels which cause difficulties to the logic testing methods based on voltage level comparison. It is shown that current testing may be an effective complement to the usual logic methods. Theoretical bounds on the coverage of single internal bridges obtainable by current testing are given.     

A path decomposition approach for computing blocking probabilitiesin wavelength-routing networks

We study a class of circuit-switched wavelength-routing networks with fixed or alternate routing and with random wavelength allocation. We present an iterative path decomposition algorithm to evaluate accurately and efficiently the blocking performance of such networks with and without wavelength converters. Our iterative algorithm analyzes the original network by decomposing it into single-path subsystems. These subsystems are analyzed in isolation, and the individual results are appropriately combined to obtain a solution for the overall network. To analyze individual subsystems, we first construct an exact Markov process that captures the behavior of a path in terms of wavelength use. We also obtain an approximate Markov process which has a closed-form solution that can be computed efficiently for short paths. We then develop an iterative algorithm to analyze approximately arbitrarily long paths. The path decomposition approach naturally captures the correlation of both link loads and link blocking events. Our algorithm represents a simple and computationally efficient solution to the difficult problem of computing call-blocking probabilities in wavelength-routing networks. We also demonstrate how our analytical techniques can be applied to gain insight into the problem of converter placement in wavelength-routing networks     

Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements

The greedy specification testing remains mandatory for analog and radio frequency (RF) integrated circuits because of the accuracy of the sorting based on these measurements. Unfortunately, to be implemented, this kind of testing method often incurs very high costs (expensive instruments, long test time…). A common approach, in the literature, is the so-called indirect/alternate test strategy. This strategy consists in deriving targeted specifications from low-cost Indirect Measurements (IMs). During the industrial test phase, the estimation of regular specifications using IMs is based on a correlation model that has been built previously, during a training phase. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is limited, mainly because of a lack of confidence in the accuracy of estimations made by the correlation model. A solution to increase the confidence in the estimation of specifications using the indirect approach is to implement redundancy in the prediction phase. In this paper, we demonstrate that the redundancy implementation brings more than identifying rare misjudged circuits from a high-correlated model. Indeed redundancy massively increases the accuracy despite of the lack of accurate models that have been assumed in previous implementations of redundant indirect testing. This approach is illustrated on a real case study for which we have experimental measurements on a set of 10,000 devices.     

计算全息图检测大口径凹非球面系统的研究

根据圆形计算全息图的衍射特性,将曲面圆形计算全息图与补偿镜相结合,应用于凹非球面折射式零检测光学系统中。与传统的折射式零检测光学系统相比,该系统不仅可以简化光学系统的装调过程,还可以降低计算全息图与补偿镜的制作精度,减少制作成本。阐述了利用曲面计算全息图衍射特性的折射式零检测光学系统检测凹非球面的基本原理,给出了具体的设计实例。对于口径为950 mm的抛物面,检测结果P-V值为0.024λ。