基于BP神经网络的大规模电路模块级故障快速诊断方法

根据大规模电路故障诊断网络撕裂法和交叉撕裂搜索方法,采用基于误差反向传播算法的多层前向神经网络(BP神经网络)记载多次撕裂信息,提出了一种新型基于BP神经网络的大规模电路模块级快速诊断方法。该方法能快速有效地并行处理定位故障模块,具有测前工作量小,实时诊断性强等优点。     

Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.     

A novel test compression algorithm for analog circuits to decrease production costs

Minimizing the manufacturing test time for ICs is one of the main keys to reducing the product cost. We introduce a methodology for automated test compression for electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find the minimum for these computationally hard integrals, which corresponds to the optimally compressed analog test. We demonstrate with an op-amp, VCO, and CMOS inverter that the method consistently reduces the length of each test by an average of 93%. Our technology can compress tests in the presence of process variation and utilize parallel processing to speed up the compression algorithm.     

Energy-aware routing in sensor networks: A large system approach

In many sensor networking environments, the sensor nodes have limited battery capacity and processing power. Hence, it is imperative to develop solutions that are energy-efficient and computationally simple. In this work, we present a simple static multi-path routing approach that is optimal in the large-system limit. In a network with energy replenishment, the largeness comes into play because the energy claimed by each packet is small compared to the battery capacity. This static routing scheme exploits the knowledge of the traffic patterns and energy replenishment statistics, but does not need to collect instantaneous information on node energy. We also develop a distributed solution of the optimal policy, as well as heuristics to build the set of pre-computed paths. The simulations verify that the static scheme outperforms leading dynamic routing algorithms in the literature, and is close to the optimal solution when the energy claimed by each packet is relatively small compared to the battery capacity.     

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout.     

大规模模拟电路故障诊断方法研究

测前工作量大和故障定位过程复杂等问题,使传统的大规模模拟电路故障诊断方法研究不再适应当前的社会发展需求,因此构建高效全面的新型故障诊断方法就变得尤为重要。本文通过对撕裂法和BP网络改进算法等新兴方法进行深入的研究,来得出其具体应用和实施的可能性。     

Synthesis method for testable electrical networks using 1st order building blocks

This work presents a method for synthesizing testable continuous-time linear time-invariant electrical networks using 1st order blocks for the implementation of analog linear circuits. A functional-structural fault model for the block, and a fault dictionary are proposed together with a simple set of test vectors. The method allows, also, the fault grade evaluation for the modeled faults. The results obtained from the two application examples have shown the suitability of the approach as a design for test method for analog circuits.     

Design of a window comparator with adaptive error threshold for online testing applications

This paper presents a novel window comparator circuit whose error threshold adjusts adaptively with respect to its input signal levels. Advantages of adaptive error thresholds over constant or relative error thresholds in analog testing applications are discussed. Analytical equations for guiding the design of the comparator circuitry are derived. The proposed comparator circuit has been designed and fabricated using a CMOS technology. Measurement results of the fabricated chip are presented.     

利用DMM比例测量法检定电阻箱程序设计

本文就传统检定电阻箱方法中存在测量误差较大、操作繁琐、效率低的问题,在介绍了DMM比例测量功能概念,比例法检定电阻箱原理、接线方法和优点的同时,提出了利用DMM比例测量功能实现检定电阻箱的方法,并描述了在LabVIEW 2011开发环境下设计检定电阻箱程序。该方法充分利用了DMM已有的测量和程控功能,除具有操作更简便,效率高和测量误差较小外,更具有易于推广应用和普及前景,对从事计量检定、自动化测量工作者具有很高的参考借鉴价值。     

一种用于APFC的模拟乘法器设计

在有源功率因数校正技术(APFC)中,通过对乘法器的输出与电感电流的峰值比较,控制功率开关管的开启与关断,使输入电流峰值包络跟随输入电压,功率因数理论上为单位值。而提高乘法器的线性度,减小非线性误差成为研究模拟乘法器的一个重要方向。本文提出的模拟乘法器采用有源衰减器显著的增大了输入信号电压范围,更重要的是在有源衰减电路中引入负反馈有效的减小了乘法器的非线性误差。基于CSMC 0.5um BCD工艺,采用Hspice进行仿真验证,在电源电压5V条件下,乘法器的一输入端的输入范围为0~2V,非线性误差小于0.6%,另一输入端的输入范围为1~4V,非线性误差小于0.3%。总谐波失真小于1.8%。     

Fuzzy optimization models for analog test decisions

Test decisions still constitute one of the most difficult and time-consuming design tasks. This is particularly true in the analog domain where some basic test questions have not yet been completely resolved. Since the gap between a good and a bad analog circuit is not always well-defined, extensive tests may result in the rejection of many fault-free ICs. The objective of this article is to propose fuzzy optimization models that can help in the more realistic formulation and resolution of the analog test problem. The set of good or fault-free ICs is considered as a fuzzy set. Each performance test is represented by a membership function. A global test measure is obtained by aggregating all the performance tests. An illustrative example using these concepts is provided.     

A path decomposition approach for computing blocking probabilitiesin wavelength-routing networks

We study a class of circuit-switched wavelength-routing networks with fixed or alternate routing and with random wavelength allocation. We present an iterative path decomposition algorithm to evaluate accurately and efficiently the blocking performance of such networks with and without wavelength converters. Our iterative algorithm analyzes the original network by decomposing it into single-path subsystems. These subsystems are analyzed in isolation, and the individual results are appropriately combined to obtain a solution for the overall network. To analyze individual subsystems, we first construct an exact Markov process that captures the behavior of a path in terms of wavelength use. We also obtain an approximate Markov process which has a closed-form solution that can be computed efficiently for short paths. We then develop an iterative algorithm to analyze approximately arbitrarily long paths. The path decomposition approach naturally captures the correlation of both link loads and link blocking events. Our algorithm represents a simple and computationally efficient solution to the difficult problem of computing call-blocking probabilities in wavelength-routing networks. We also demonstrate how our analytical techniques can be applied to gain insight into the problem of converter placement in wavelength-routing networks     

适用于模数统一测试的故障隔离方法

介绍了一种实用的故障隔离方法及其实现。该方法既适用于模拟电路又适用于数字电路的故障隔离,已成功用于模数混合电路单元故障诊断系统。     

Current testing in dynamic CMOS circuits

Current testing of dynamic CMOS integrated circuits with single phase clock is investigated. The analysis is performed on a single phase stage dynamic module in the presence of internal bridging defects of low resistance. These defects produce intermediate voltage levels which cause difficulties to the logic testing methods based on voltage level comparison. It is shown that current testing may be an effective complement to the usual logic methods. Theoretical bounds on the coverage of single internal bridges obtainable by current testing are given.     

Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements

The greedy specification testing remains mandatory for analog and radio frequency (RF) integrated circuits because of the accuracy of the sorting based on these measurements. Unfortunately, to be implemented, this kind of testing method often incurs very high costs (expensive instruments, long test time…). A common approach, in the literature, is the so-called indirect/alternate test strategy. This strategy consists in deriving targeted specifications from low-cost Indirect Measurements (IMs). During the industrial test phase, the estimation of regular specifications using IMs is based on a correlation model that has been built previously, during a training phase. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is limited, mainly because of a lack of confidence in the accuracy of estimations made by the correlation model. A solution to increase the confidence in the estimation of specifications using the indirect approach is to implement redundancy in the prediction phase. In this paper, we demonstrate that the redundancy implementation brings more than identifying rare misjudged circuits from a high-correlated model. Indeed redundancy massively increases the accuracy despite of the lack of accurate models that have been assumed in previous implementations of redundant indirect testing. This approach is illustrated on a real case study for which we have experimental measurements on a set of 10,000 devices.     

晶体管HFE参数的快速测试方法

随着国内半导体分立器件生产规模的发展,晶体管生产厂家及使用单位对晶体管测试速度的要求越来越高,而制约测试速度最主要的因素就是HFE参数的测试速度远远达不到现在生产的需要。本文在探讨晶体管HFE参数的通用测试方法不足的基础上,提出晶体管HFE参数先进的快速测试方法。依据此方法并结合现有半导体分立器件测试系统,主要通过硬件配合在测试系统内构造出晶体管HFE参数的快速测试单元,把测试速度由原来的1000ms提高到15ms,实现了从测试方法到技术成果的转化。     

大口径非球面计算全息图检测系统

为了精确地检测大口径非球面面形质量,将曲面圆形计算全息图与补偿镜相结合,应用于非球面折射式检测光学系统中.分析了曲面计算全息图的衍射特性,同时分别阐述了利用曲面计算全息图的这种衍射特性来检测凹非球面及凸非球面的基本原理和方法,给出了具体的设计实例.与传统的非球面检测光学系统相比较,该系统不仅简化了传统光学系统的装调过程,还可以大大降低计算全息图（CGH）与补偿镜的制作精度,减少制作成本.尤其是在凸非球面检测过程中,首次在实验技术方面提出了两步全孔径检测法和调整误差的旋转相减消除法,实验验证了该方法的有效性.     

A Lagrangean relaxation approach for QoS networks CFA problems

This paper is about design methodologies for packet networks, under the constraints of end-to-end quality of service (QoS) metrics. The network modeling also considers the dynamics of today's packet networks. We are particularly considering the problem of capacity and flow assignment where the routing assignments and capacities are considered to be decision variables. An efficient Lagrangean relaxation-based heuristic procedure is developed to find bounds and solutions for a corporate virtual private network (VPN), where the traffic is mostly based on TCP connections. Numerical results for a variety of problem instances are reported.     

某型试验指挥系统的软件测试方法

随着军用软件在军事装备中的规模、比例的不断增大,军用软件对武器装备作战使用效能的发挥起着举足轻重的作用,从某型试验指挥系统软件设计原理和功能需求入手,设计了具体的测试方法,经过测试,保证了该型试验指挥系统软件的长期稳定可靠运行,对现在军用软件的测试方法的改进有一定的借鉴作用。     

A survey on fault diagnosis of analog circuits: Taxonomy and state of the art

Due to the wide range of applications of electronic circuits in the recent years, the fault diagnosis in electronic circuits is a foremost problem. The main purpose of the fault diagnosis technique is isolating the faults present in the electronic circuits and also, detecting the fault which affects the safety and performance of the system. For various real-time applications of fault diagnosis, literature presents several techniques for detecting the faults in electronic circuits. In this paper, reviews on the research based on the fault diagnosis techniques which are all gained much attention are comprehended. Accordingly, 114 research papers related to the fault diagnosis are reviewed and analyzed based on the various objectives. In this review, we present the taxonomy of the fault detection in analog circuits and discuss the state of the art algorithms with various advantages and major drawbacks. The comprehensive analysis is carried out on finding the coverage of the publishers, faults, circuits, methods, simulation tools, and metrics. This critical review finally discusses the research challenges that are still available in the existing techniques and the way to extend the current research is also examined.