Numerical simulation of GaAs MESFETs with a p-buffer layer on asemi-insulating substrate compensated by deep traps

A numerical analysis of GaAs MESFETs with a p-buffer layer on a semi-insulating substrate is performed in which impurity compensation by traps in the substrate is considered. It is shown that the use of a thick p-buffer layer results in a lower device current due to the formation of a steep barrier at the channel-substrate interface. It is also shown that with higher trap and acceptor densities in the substrate, the drain current is reduced due to the decrease in the substrate current. This decrease occurs because a negative-space-charge layer is formed in the substrate. It is demonstrated that when the p-buffer layer is fully depleted, its acceptors play the same electrical role as the acceptors within the space-charge region of the semi-insulating substrate. Thus, using a thick p-buffer layer has the same effect as using a substrate with a high density of traps, i.e. it minimizes the short-channel effects in GaAs MESFETs. Therefore, if the trap density in the substrate is low, the short-channel effects can be reduced by introducing a p-buffer layer or a buried p-layer     

A back-wafer contacted silicon-on-glass integrated bipolar process. Part I. The conflict electrical versus thermal isolation

A novel silicon-on-glass integrated bipolar technology is presented. The transfer to glass is performed by gluing and subsequent removal of the bulk silicon to a buried oxide layer. Low-ohmic collector contacts are processed on the back-wafer by implantation and dopant activation by excimer laser annealing. The improved electrical isolation with reduced collector-base capacitance, collector resistance and substrate capacitance, also provide an extremely good thermal isolation. The devices are electrothermally characterized in relationship to different heat-spreader designs by electrical measurement and nematic liquid crystal imaging. Accurate values of the temperature at thermal breakdown and thermal resistance are extracted from current-controlled Gummel plot measurements.     

Backside copper metallization of GaAs MESFETs using TaN as thediffusion barrier

Backside copper metallization of GaAs MESFETs using TaN as the diffusion barrier was studied. A thin TaN layer of 40 nm was sputtered on the GaAs substrate before copper film metallization, as judged from the data of X-ray diffraction (XRD), Auger electron spectroscopy (AES), and cross-sectional transmission electron microscopy (TEM), the Cu/TaN films with GaAs were very stable without interfacial interaction up to 550°C annealing; the copper metallized MESFETs were thermally stressed at 300°C. The devices showed very little change in the device characteristics (<3%) after thermal stress, and the changes of the electrical parameters and RF characteristics of the devices after thermal stress were of the same order as those devices without Cu metallization, these results show that TaN is a good diffusion barrier for Cu in GaAs devices and the Cu/TaN films can be used for the backside copper metallization of GaAs MESFETs     

High-temperature electrical characteristics of GaAs MESFETs(25-400°C)

The effects of elevated ambient and substrate temperatures (25°C up to 400°C) on the electrical characteristics of integrated GaAs MESFETs in a state-of-the-art commercial technology are reported. The focus is on the large- and small-signal parameters of the transistors. The existence of zero-temperature-coefficient drain currents is demonstrated analytically and experimentally for enhancement- and for depletion-mode GaAs MESFETs. The data show that, while GaAs MESFETs generally display degradation mechanisms similar to those of silicon MOSFETs with increasing temperature, they incur several additional effects, prominent among which are increased gate leakage currents, lowered Schottky-barrier height, decreased large- and small-signal (gate) input resistances, decreased sensitivity to sidegating and backgating up to approximately 200°C, and increased small-signal drain resistance     

Sidegating effect of GaAs MESFETs in carbon doped GaAs substrate

The sidegating effect of GaAs MESFETs in carbon doped semi-insulating GaAs substrate was investigated. Measurement results suggest that both the hole injection at one part of the gate electrode, and the modulation of the width of the depletion layer near the interface between the channel and substrate, cause the sidegating effect of GaAs MESFETs. Also, with the increase of carbon concentration, the latter cause becomes dominant in the sidegating effect.<>     

Improvement of RF performance of GaAs/Si MESFETs using buriedoxygen implantation

A novel buried oxygen implantation (BOI) procedure is described to reduce parasitics and improve RF performance of GaAs/Si MESFETs. Devices fabricated with this procedure show output conductance of less than 8.5 mS/mm which is the lowest reported to date for GaAs/Si MESFETs. These results are particularly important to improve the power performance of GaAs/Si MESFETs     

DC and RF performance of GaAs MESFET fabricated on silicon substrate using epitaxial lift-off technique

GaAs MESFETs have been fabricated on a silicon substrate using a molecular beam epitaxy grown film detached from its growth substrate and attached on a silicon substrate covered with a dielectric. The device processing is done on the silicon substrate. The MESFETs exhibit I/sub DSS/=130 mA/mm, g/sub m/=135 mS/mm and for 1.3 mu m gate length unity current gain cut-off frequency f/sub T/ of 12 GHz. Excellent device isolation with subpicoampere leakage currents is obtained.<>     

RF and 1/f noise investigations on MESFETs and circuitstransplanted by epitaxial lift off

In this paper, we present the results of RF and noise measurements of MESFETs transplanted by epitaxial lift off (ELO). ELO is a technology by which epitaxially grown layers are lifted off from their growth substrate and subsequently reattached to a new host substrate. In the experiments described here a 800 mm thick GaAs film containing MESFETs or complete microwave circuits is transplanted onto semi-insulating InP. Gate leakage current, RF characteristics, and noise performance of MESFETs and GaAs circuits are compared before and after ELO. Special attention was given to low-frequency (1/f) noise, 1/f noise is believed to be caused by surface as well as bulk effects. An increase in 1/f noise could have been predicted since a new surface is exposed during the transplantation process. The mechanical stress during the transplantation could cause crystal damage creating additional traps which could also result in an increase in 1/f noise     

Two-dimensional analysis of short-channel delta-doped GaAs MESFETs

Key design parameters for delta-doped GaAs MESFETs, such as delta doping profile, top layer background doping density, and scaling of lateral feature size, are investigated using a two-dimensional numerical simulation. A three-region (delta-doped conducting channel, top layer, and substrate) velocity-field relation is implemented in the model as appropriate for the particular device structure which is simulated. Simulation results show excellent agreement with a fabricated 0.5-μm gate-length delta-doped GaAs MESFETs based on atomic layer epitaxy material. An extrinsic transconductance of 370 mS/mm and a drain-source current of 270 mA/mm are obtained for typical devices, and the maximum transconductance is as high as 400 mS/mm. These are the best DC results yet reported for 0.5-μm gate-length delta-doped GaAs MESFETs. Considerations of design and optimization are discussed in terms of threshold voltage sensitivity, transconductance, current drive capability, and cutoff frequency, based on both simulation and experiment results     

A possible scaling limit for enhancement-mode GaAs MESFETs in DCFLcircuits

A possible scaling limit for ion-implanted GaAs MESFETs with buried p-layer LDD structure has been numerically investigated. A Schottky-contact model with a thin interfacial layer and interface states was used to simulate the Schottky-barrier height of a scaled-down MESFETs. When enhancement-mode MESFETs in direct-coupled FET logic (DCFL) circuits are scaled down, the gate length can be reduced to 0.21 μm at an interface-state density of 6.6×10¹² cm^-2·eV^-1, when the barrier height is greater than 0.6 V, the threshold voltage is less than 0.1 V, and the channel aspect ratio is 8     

Model for photo-induced long-term drain current transients in GaAs MESFETs

A simple model is presented for the negative drain current transients observed in GaAs MESFETs when subjected to ionizing radiation. The two dominant mechanisms are proposed to be electron trapping under the Schottky gate and in the neutral semi-insulating substrate. The model is suitable for the design and evaluation of radiation-resistant GaAs MESFET integrated circuits using common electrical simulators such as SPICE3.     

Numerical analysis of GaAs MESFETs with p-buffer layer on semi-insulating substrate including deep traps

Numerical analysis of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate is presented in which impurity compensation by traps is included. Using a p-buffer layer is shown to be effective in minimising the short-channel effects as in the case of using a substrate with high density of traps.<>     

Effects of neutral buried p-layer on high-frequency performance ofGaAs MESFETs

Fully ion-implanted n⁺ self-aligned GaAs MESFETs with Au/WSiN refractory metal gates have been fabricated by adopting neutral buried p-layers formed by 50-keV Be-implantation. S-parameter measurements and equivalent circuit fittings are discussed. When the Be dose is increased from 2×10¹² cm^-2 to 4×10¹² cm^-2, the maximum value of the cutoff frequency with a 0.2-μm gate falls off from 108 to 78 GHz. This is because a neutral buried player makes the intrinsic gate-source capacitance increase markedly, while its influence on gate-drain capacitance and gate-source fringing capacitance is negligible. The maximum oscillation frequency recovers, however, due primarily to the drain conductance suppression by the higher-concentration buried p-layer. An equivalent value of over 130 GHz has been obtained for both 0.2-μm-gate GaAs MESFETs     

Proton-bombardment isolated GaAlAs/GaAs charge-coupled devices

Proton bombardment is used for the first time as a channel isolation technique to fabricate buried channel homojunction charge-coupled devices (c.c.d.s) of n-GaAs channel on GaAs substrate and heterojunction c.c.d.s of n-Ga1?xAlxAs on GaAs. The c.c.d. structure is a Schottky-barrier gate buried channel 3-phase device with 30 transfer gates. The channel-stop bombardment was carried out at room temperature with an energy of 200 keV and a total dose of 1015/cm2. The c.c.d.s were tested with electrical charge injection and direct readout. The charge transfer efficiency was found to be greater than 0.999 per transfer for both GaAs and GaAlAs. The proton-bombardment isolated devices were compared with similar devices using mesa isolation and were found to perform similarly.     

Numerical analysis of the photoeffects in GaAs MESFET's

The photoeffects on the I-V characteristics of GaAs MESFETs have been studied by a two-dimensional numerical method. It is theoretically verified that the photovoltaic effect occurring at the channel/substrate interface is responsible for the substantial increase of the drain current. The reverse gate current due to illumination is caused by sweep-out by the high electrical field in the gate depletion region, where a large gradient in the depth profile of the hole Fermi energy is found. For devices with a lightly doped n-type buffer layer, the increase of the drain current is less than for devices without a buffer layer, but is still substantial     

Junction-isolated electrical test structures for critical dimension calibration standards

The National Institute of Standards and Technology (NIST) is developing single-crystal reference materials for use as critical dimension (CD) reference materials. In earlier work, the reference features on these reference materials have been patterned in the device layer of a silicon-on-insulator (SOI) wafers, with the buried oxide providing electrical isolation. This paper describes a new method of isolating the structures from the substrate by means of a pn junction. The junction isolation technique is expected to provide several advantages over the SOI technique including minimal susceptibility to charging when imaged in a CD scanning electron microscope (CDSEM), better edge quality, and ease of manufacture. Primary calibration of these reference materials is by imaging the cross-section of the feature with high-resolution transmission electron microscopy (HRTEM) at sufficiently high energy to resolve and count the individual lattice planes while electrical test structure metrology techniques provide the transfer calibration. Secondary calibration is performed with electrical test structure metrology, supplemented by visual techniques to verify that the features meet uniformity requirements. In this paper, we describe results for determining the electrical critical dimensions of these junction-isolated structures. This measurement and data analysis technique is a unique combination of the short-bridge variation of the cross-bridge resistor and the multi-bridge structure.     

Study of novel techniques for reducing self-heating effects in SOI power LDMOS

Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.     

发展中的RF MEMS开关技术

射频MEMS开关是用MEMS技术形成的新的电路元件,与传统的半导体开关器件相比具有插入损耗低、隔离度大、线性度好等优点,将对现有雷达和通信中RF结构产生重大的影响。介绍了射频MEMS开关的工作原理、优化设计,分析了可靠性问题,举例说明了射频MEMS开关的应用,指出了其发展所面临的问题。     

发展中的RF MEM5开关技术

射频MEMS开关是用MEMS技术形成的新的电路元件,与传统的半导体开关器件相比具有插入损耗低、隔离度大、线性度好等优点,将对现有雷达和通信中RF结构产生重大的影响.介绍了射频MEMS开关的工作原理、优化设计,分析了可靠性问题,举例说明了射频MEMS开关的应用,指出了其发展所面临的问题.     

Double heterostructure Ga0.47In0.53As MESFETs with submicron gates

MESFETs with GA0.47In0.53As active channel grown by MBE on InP substrates were successfully fabricated. Thin layers of MBE grown Al0.48In0.52As seperated both the single crystal aluminum gate from the active channel and the active channel from the InP substrate so raising the Schottky barrier height of the gate and confining the electrons to the channel. The MESFETs with 0.6µm long gates and gate-to-source separations of 0.8 um exhibited an average gmof 135 mS mm^-1of gate width for Vds= 2V and Vg= 0. This is higher than that reported for GaAs MESFETs with a similar geometry in spite of the intermediate layer between the gate metal and the active layer.