Differential current-sensing for on-chip interconnects

This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increase in wire width. Unlike repeaters, current-sensing does not require placement of buffers along the wire, and hence, eliminates any placement constraints. Inductive effects are negligible in differential current-sensing. Current-sensing also provides a tighter bound on delay with respect to process variations. However, current-sensing has some drawbacks. It is power inefficient due to the presence of static-power dissipation. Current-sensing is essentially a low-swing signaling technique, and hence, it is sensitive to full swing aggressor noise.     

Stacked polymeric multimode waveguide arrays for two-dimensional optical interconnects

Two-dimensional (2-D) polymeric multimode waveguide arrays with two reflection-mirrors have been fabricated for optical interconnects between 2-D arrayed vertical-cavity surface-emitting lasers and detectors. Contact printing lithography was adopted for simple and low-cost process using ultraviolet-curable epoxy-based polymers. Fabricated waveguides were diced of the same size and stacked one by one with lateral positional errors less than /spl plusmn/20 /spl mu/m. Two kinds of mirrors were fabricated: single-reflection mirror and double-reflection mirror. Double-reflected mirrors resulted in lower losses with 1.2 dB than single reflected mirrors with 2.1 dB. The average insertion losses of 16-channel arrayed waveguides with two single-reflection mirrors and with two double-reflection-mirrors were measured to be 6.1 and 4.4 dB for 6-cm-long waveguides at a wavelength of 830 nm, respectively. The crosstalk between the waveguides was less than -25 dB. The characteristics of the waveguide arrays are good enough for applications to optical interconnects.     

Guided-wave planar optical interconnects using highly multiplexedpolymer waveguide holograms

An intraplanar interconnection scheme using substrate guided modes in conjunction with a highly multiplexed waveguide volume hologram is proposed. Acoustooptically addressed 1-to-50 passive and 1-to-2-to-100 reconfigurable interconnections with a fan-out diffraction efficiency of 55% at 514-nm wavelength are demonstrated. A coordinate transformation converts the 3-D diffraction problem into a 2-D one, which significantly simplifies the theoretical calculation. Intraplane massive fan-out optical interconnection using substrate guided mode provides both collinear and coplanar fan-out capability for data and clock signals. Colinearity of signal distribution allows the 2-D input signal array to be processes. The laminated waveguide device containing a highly multiplexed dichromated gelatin (DCG) hologram has been evaluated     

Electromigration challenges for advanced on-chip Cu interconnects

As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures taken by the interconnect process development, circuit design and chip integration to overcome this challenge. While innovative process integration schemes, especially direct and indirect Cu/cap interface engineering, have proven effective to suppress Cu diffusion and enhance the EM performance, the strategies for circuit/chip designs to take advantage of specific layout and EM failure characteristics are equally important to ensure overall EM reliability and optimized performance. To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration.     

Design and fabrication of low-loss polymer waveguide components for on-chip optical interconnection

This paper reports the fabrication and characterization of straight and curved polyimide waveguides for on-chip optical signal distribution in GaAs-based optoelectronic integrated circuits. Polyimide ridge waveguides with propagation losses (at 830 nm) as low as 0.6 dB/cm have been fabricated. S-bends and splitters with low curvature losses and good splitting ratios have also been successfully fabricated and tested. The effects of the material properties and radius of curvature on the optical losses are presented, and the advantages of this polymer technology are discussed.     

Flexible optical waveguide film fabrications and optoelectronic devices integration for fully embedded board-level optical interconnects

This paper demonstrates a flexible optical waveguide film with integrated optoelectronic devices (vertical-cavity surface-emitting laser (VCSEL) and p-i-n photodiode arrays) for fully embedded board-level optical interconnects. The optical waveguide circuit with 45/spl deg/ micromirror couplers was fabricated on a thin flexible polymeric substrate by soft molding. The 45/spl deg/ couplers were fabricated by cutting the waveguide with a microtome blade. The waveguide core material was SU-8 photoresist, and the cladding was cycloolefin copolymer. A thin VCSEL and p-i-n photodiode array were directly integrated on the waveguide film. Measured propagation loss of a waveguide was 0.6 dB/cm at 850 nm.     

High-speed completion detection for current sensing on-chip interconnects

A novel completion detection technique for delay insensitive current sensing on-chip interconnects is presented. The scheme is based on sensing currents on the data wires and comparing the sum of these currents to an appropriately set reference. The goal is to solve the performance bottleneck caused by conventional voltage-mode detection methods. With the channel width of 64 bits, the proposed method is 4.65 times faster and takes 36% less area than the voltage-mode scheme. Furthermore, its speed does not degrade when increasing the channel bit width. It is implemented in a 65 nm CMOS technology.     

Analysis of integrated optical waveguide mirrors

A new method is presented to analyze reflection losses of integrated mirrors, taking into account the exact guided mode profile and assuming that this profile remains unchanged up to the reflecting plane. The fraction of the reflected light coupled to one of the guided modes of the output waveguide is calculated, taking into account the mirror reflection coefficient. The influence of both translation and tilt of the reflecting plane is investigated. The method applies for every guided mode and any reflection angles. Numerical calculations are derived for a 90° optical corner mirror     

A unified RLC model for high-speed on-chip interconnects

In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width (W/sub eff/) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new analytical "wall-to-wall" model. The effective width provides a physics-based approach to decompose any 3-D structure into a series of 2-D segments, resulting in an efficient and accurate capacitance extraction. In the inductance model, we use an effective loop inductance approach for an analytic and hierarchical model construction. In particular, we show empirically that high-frequency signals (above multi-GHz) propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance from the capacitance of the wire. Finally, the capacitance and inductance models are combined into a unified frequency-dependent RLC model, describing successfully the wide-band characteristics of on-chip interconnects up to 100 GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model.     

Designing fast on-chip interconnects for deep submicrometer technologies

This paper proposes a solution to the problem of improving the speed of on-chip interconnects, or wire delay, for deep submicron technologies where coupling capacitance dominates the total line capacitance. Simultaneous redundant switching is proposed to reduce interconnect delays. It is shown to reduce delay more than 25% for a 10-mm long interconnect in a 0.12-/spl mu/m CMOS process compared to using shielding and increased spacing. The paper also proposes possible design approaches to reduce the delay in local interconnects.     

High-frequency characterization of on-chip digital interconnects

On-chip inductance is becoming increasingly important as technology continues to scale. This paper describes a way to characterize inductive effects in interconnects. It uses realistic test structures that study the effect of mutual couplings to local interconnects, to random lines connected to on-chip drivers, and to typical power and ground grids. The use of S parameters to characterize the inductance allows a large number of lines to be extracted while requiring only a small overhead measurement of dummy open pads to remove measurement parasitics. It also enables direct extraction of the frequency-dependent R, L, G, C parameters. The results are summarized with curve-fitted formulas of inductance and resistance over a wide range of line spacings and line widths. The significance of the frequency dependence is illustrated with transient analysis of a typical repeater circuit in a 0.25-μm technology. A model that captures the frequency dependency of the extracted parameters accurately predicts the performance of a new inductance-sensitive ring oscillator     

50-GHz integrated interconnects in silicon optical microbench technology

A custom-designed silicon-based 50-GHz interconnect is integrated for packaging demonstrations of broadband optoelectronic (OE) applications in silicon optical microbench technology. The half-shielded (or partially shielded) 0.5-cm interconnect has 25-dB isolation and 0.9-dB transmission loss over 50 GHz. When implemented in this packaged architecture, the nature of the interconnect minimizes coupling and eliminates the need for an external test fixture that is prevalent in a more conventional approach. The interconnect is further demonstrated in a multiport electrical package to illustrate the potential of this architecture up to 40-Gb data rates, and the resulting package has insertion loss less than 5 dB at 50 GHz.     

Loop-based inductance extraction and modeling for multiconductor on-chip interconnects

An efficient extraction and modeling methodology for self and mutual inductances within multiconductors for on-chip interconnects is investigated. The method is based on physical layout considerations and current distribution on multiple return paths, leading to loop inductance and resistance. It provides a lumped circuit model suitable for timing analysis in any circuit simulator, which can represent frequency-dependent characteristics. This novel modeling methodology accurately provides the mutual inductance and resistance as well as self terms within a wide frequency range without using any fitting algorithm. Measurement results for single and coupled wires within a multiconductor system, fabricated using 0.13 and 0.18 /spl mu/m CMOS technologies, confirm the validity of the proposed method. Our methodology can be applicable to high-speed global interconnects for post-layout as well as prelayout extraction and modeling.     

Comparisons of conventional, 3-D, optical, and RF interconnects for on-chip clock distribution

This paper analyzes the performance of different interconnect technologies for on-chip clock distribution, including conventional, three-dimensional, optical, and radio frequency interconnects. Skew, power, and area usage were estimated for each of these technologies based on the 2001 International Technology Roadmap for Semiconductors. Our results indicate that most of the skew and power are associated with local clock distribution. Consequently, since the alternative clock distribution approaches that have been proposed focus on global clock distribution, we have not found significant advantages over conventional clock distribution in terms of skew and power. Furthermore, it was found that low skews could be attained with conventional clock distribution schemes if the clock signals are not scaled down.     

A design-oriented methodology for accurate modeling of on-chip interconnects

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.     

SPICE compatible modelling of on-chip coupled interconnects

On-chip coupled interconnect lines are modelled using measured S-parameters. The physical consistency between single and coupled line model parameters are maintained in the proposed methodology. The SPICE compatible model is validated in both the frequency and the time domain using copper and ultra low-kappa coupled interconnects.     

Near speed-of-light signaling over on-chip electrical interconnects

The propagation limits of electrical signals for systems built with conventional silicon processing are explored. A design which takes advantage of the inductance-dominated high-frequency regime of on-chip interconnect is shown capable of transmitting data at velocities near the speed of light. In a 0.18-/spl mu/m six-level aluminum CMOS technology, an overall delay of 283 ps for a 20-mm-long line, corresponding to a propagation velocity of one half the speed of light in silicon dioxide, has been demonstrated. This approach offers a five times improvement in delay over a conventional repeater-insertion strategy.     

Fabrication and characterization of polymer optical waveguides with integrated micromirrors for three-dimensional board-level optical interconnects

This paper describes the fabrication and characterization of optical/electrical printed circuit boards (O/E-PCB) with embedded multimodal step index (MM-SI) waveguides and integrated out-of-plane micromirrors (IMMs) for three-dimensional (3-D) optical interconnects. Optical circuitry is built up on PCBs using UV lithography; 45/spl deg/ input/output (I/O) couplers are fabricated by inclined exposure. Commercial polymers are used as optical core and cladding materials. Critical mirror properties of angle, surface quality, reflectivity, and coupling efficiency are characterized experimentally and theoretically. Optical and scanning electron microscopy, white light interferometry, and fiber scanning method are used in the investigations. Sloping profiles measured as a function of the incident light showed the attainment of mirror angles of /spl alpha/=36/spl deg/-45/spl deg/ with /spl plusmn/2/spl deg/ consistency. Near-field optical imaging with a white light source showed that out-of-plane beam turning was achieved. Topography investigations revealed a rectilinear negative tapering shape regardless of the incoming beam angle or type of substrate. However, higher substrate reflectancy was observed to lower the mirror angle. The average propagation loss measured for 10-cm-long waveguides at /spl lambda/=850 nm by the cut-back method was 0.60 dB/cm; the excess loss calculated for the mirror coupling was 1.8-2.3 dB. The results showed that the IMMs can be incorporated in O/E-PCBs to couple light in and out of planar waveguides. Furthermore, the presented results indicate that optical waveguides with integrated micromirrors for optical 3-D wiring can be produced compatible with volume manufacturing techniques.