Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

The authors have proved that negative bias temperature instability (NBTI) is an important reliability issue in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The measurements revealed that the threshold-voltage shift is highly correlated to the generation of grain-boundary trap states. Both these two physical quantities follow almost the same power law dependence on the stress time; that is, the same exponential dependence on the stress voltage and the reciprocal of the ambient temperature. In addition, the threshold-voltage shift is closely associated with the subthreshold-swing degradation, which originates from dangling bond formation. By expanding the model proposed for bulk-Si MOSFETs, a new model to explain the NBTI-degradation mechanism for LTPS TFTs is introduced     

Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in LTPS TFTs. That is, when performing the NBTI measurement, the LTPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the LTPS TFT circuitry design     

Dynamic Negative Bias Temperature Instability (NBTI) of Low-Temperature Polycrystalline Silicon (LTPS) Thin-Film Transistors

The dynamic negative bias temperature instability (NBTI) on low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated in detail. Experimental results revealed the threshold voltage shift of LTPS TFTs after the NBTI stress decreases with increasing frequency, which is different from the frequency-independence of conventional CMOSFET. Under a low frequency stress, the capacitance-voltage measurement with various frequencies implied that a larger quantity of inversion holes was trapped in the grain boundary. Thus, the difference of the transit time between the grain boundary and interface dominates the LTPS TFTs dynamic NBTI behaviors and results in the dependence of frequency.     

Negative Bias Temperature Instability Dominated Degradation of Metal-Induced Laterally Crystallized p-Type Polycrystalline Silicon Thin-Film Transistors

Device degradation of solution-based metal-induced laterally crystallized p-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is studied under dc bias stresses. While typical negative bias temperature instability (NBTI) or electron injection (EI) is observed under $-V_{g}$ or $-V_{d}$ only stress, respectively, no typical hot carrier (HC) degradation can be identified under high $-V_{d}$ stress combined with either low or high $-V_{g}$ stress. Instead, mixed NBTI and EI degradation is observed under combined low $-V_{g}$ and $-V_{d}$ stresses; and combined degradation of NBTI and HC occurs under high $-V_{d}$ and moderate $-V_{g}$ stresses. NBTI is the dominant mechanism in both cases. Grain boundary (GB) trap generation is found to correlate with the NBTI degradation with the same time exponent, suggesting the key role of GB trap generation in poly-Si TFTs' degradation.      

A Reliability Model for Low-Temperature Polycrystalline Silicon Thin-Film Transistors

We proposed here a reliability model that successfully introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.      

Low-Temperature Polycrystalline Silicon Thin-Film Flash Memory With Hafnium Silicate

In this paper, we have successfully fabricated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type poly-Si-thin-film transistor (TFT) memories employing hafnium silicate as the trapping layer with low-thermal budget processing (les600degC). It was demonstrated that the fabricated memories exhibited good performance in terms of relatively large memory window, high program/erase speed (1 ms/10 ms), long retention time (>10⁶ s for 20% charge loss), and 2-bit operation. Interestingly, we found that these memories depicted very unique disturbance behaviors, which are obviously distinct from those observed in the conventional SONOS-type Flash memories. We thought these specific characteristics are closely related to the presence of the inherent defects along the grain boundaries. Therefore, the elimination of the traps along the grain boundaries in the channel is an important factor for achieving high performance of the SONOS-type poly-Si-TFT Flash memory     

Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler–Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel–Poole emission.      

Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses

Device degradation behaviors of typical-sized n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors were investigated in detail under two kinds of dc bias stresses: hot-carrier (HC) stress and self-heating (SH) stress. Under HC stress, device degradation is the consequence of HC induced defect generation locally at the drain side. Under a unified model that postulates, the establishment of a potential barrier at the drain side due to carrier transport near trap states, device degradation behavior such as asymmetric on current recovery and threshold voltage degradation can be understood. Under SH stress, a general degradation in subthreshold characteristic was observed. Device degradation is the consequence of deep state generation along the entire channel. Device degradation behaviors were compared in low V_d-stress and in high V_d-stress condition. Defect generation distribution along the channel appears to be different in two cases. In both cases of SH degradation, asymmetric on current recovery was observed. This observation, when in low V_d-stress condition, is tentatively explained by dehydrogenation (hydrogenation) effect at the drain (source) side during stress     

Characteristics and Fluctuation of Negative Bias Temperature Instability in Si Nanowire Field-Effect Transistors

In this letter, negative bias temperature instability (NBTI) in silicon nanowire field-effect transistors (SNWFETs) is investigated and found to exhibit some new characteristics that are probably due to the structural nature of nanowires. In long-channel SNWFETs, a fast degradation and a quick saturation of NBTI are observed and discussed. In short-channel SNWFETs, a large fluctuation of NBTI is observed, which mainly originates from the ultrasmall gate areas of the short-channel SNWFETs and the statistical nature of randomly trapped charges in the oxide and at the Si/SiO₂ interface. Techniques to suppress the fluctuation and characterize the intrinsic NBTI in ultrasmall SNWFETs are proposed and discussed. A recently developed online gate current method is demonstrated, which effectively alleviates this NBTI fluctuation in SNWFETs.     

Low-Temperature Pulsed-PECVD ZnO Thin-Film Transistors

We report high-quality ZnO thin films deposited at low temperature (200°C) by pulsed plasma-enhanced chemical vapor deposition (pulsed PECVD). Process byproducts are purged by weak oxidants N₂O or CO₂ to minimize parasitic CVD deposition, resulting in high-refractive-index thin films. Pulsed-PECVD-deposited ZnO thin-film transistors were fabricated on plasma-enhanced atomic layer deposition (PEALD) Al₂O₃ dielectric and have a field-effect mobility of 15 cm²/V s, subthreshold slope of 370 mV/dec, threshold voltage of 6.6 V, and current on/off ratio of 10⁸. Thin-film transistors (TFTs) on thermal SiO₂ dielectric have a field-effect mobility of 7.5 cm²/V s and threshold voltage of 14 V. For these devices, performance may be limited by the interface between the ZnO and the dielectric.     

Dynamic Bias Instability of p-Channel Polycrystalline-Silicon Thin-Film Transistors Induced by Impact Ionization

The dynamic stress switching of p-channel polycrystalline-silicon (poly-Si) thin-film transistors from full depletion to accumulation bias creates the high electric field near source/drain (S/D) junctions due to the slow formation of the accumulated electrons at the $hbox{SiO}_{2}/hbox{poly}$ -Si interface. The high electric field causes impact ionization near the S/D, where the secondary electrons surmount the $hbox{SiO}_{2}$ barrier and are trapped near the interface. The channel region near the S/D is inverted to p-type by the trapped electrons, and the effective channel length is reduced. The drain current increases with the stress time, particularly for short-channel devices.      

Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Using a fluorinated high-k/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-k deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-fc is a concern. The novel fluorinated Ta_infinC_y/HfZrO_infin/SRPO gate stack device exceeds the positive-bias-temperature-instability and negative-bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon.     

Performances of a Capacitorless 1T-DRAM Using Polycrystalline Silicon Thin-Film Transistors With Trenched Body

Polycrystalline silicon thin-film transistors (TFTs) can be improved by integrating DRAM on chip. However, the TFT's poor capacitance means that traditional DRAMs are infeasible, because they require a capacitor. An alternative, the one-transistor DRAM (1T-DRAM), is promising because it avoids the capacitor by instead storing the logical value as holes trapped in the body region. This letter proposes the use of a trenched body in a TFT to construct a 1T-DRAM. Previously, we have shown that a trenched body reduces the leakage current of a TFT. In this letter, we now show that the trenched-body TFT also works well as a 1T-DRAM device. It has a strong back-gating effect and a programming window that is more than twice as large as that of the conventional TFT.      

纳米PMOSFET负偏压温度不稳定性测试方法

P型金属氧化物半导体场效应晶体管(PMOSFET)的负偏压温度不稳定性(NBTI)是制约纳米MOS器件在长寿命电子系统中应用的关键问题之一。为了准确地表征NBTI效应对器件参数的影响,分析了现有测试方法的特点,在此基础上改进了测试试验方法。利用该方法对90nm体硅工艺器件的NBTI效应进行了测试和分析,结果表明该方法能够很好地避免间断应力方法造成的参数快速恢复,获得更加准确的试验数据。     

A Reduced Mask-Count Technology for Complementary Polycrystalline Silicon Thin-Film Transistors With Self-Aligned Metal Electrodes

The inexpensive glass substrate for building conventional low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) imposes a ceiling on the TFT processing temperature. This results in a reduced efficiency of dopant activation and a high source/drain series resistance. A technique based on aluminum-induced crystallization of amorphous silicon has been applied to fabricate TFTs with low-resistance self-aligned metal electrodes (SAMEs). While at least two masked implantation steps are typically used for constructing the doped source and drain regions of conventional n- and p-channel TFTs in a complementary metal–oxide–semiconductor circuit technology, it is currently demonstrated that complementary SAME poly-Si TFTs can be constructed using a combination of a masked and a blanket source and drain implantation steps. The decrease in mask count reduces process complexity and cost. Control of ion channeling is the enabling factor behind the successful demonstration of the technology.      

基于高迁移率微晶硅的薄膜晶体管

近年来,微晶硅(μc-Si:H)被认为是一种制作 TFT 的有前景的材料.采用PECVD法,在低于200℃时制作了微晶硅TFTs,其制作条件类似于非晶态 TFTs.微晶硅 TFTs 器件的迁移率超过了 30 cm2/Vs,而阈值电压是 2.5 V.在长沟道器件(50～200 μm)中观测到了这种高迁移率.但对于短沟道器件(2 μm),迁移率就降低到了7 cm2/Vs.此外,该 TFTs 的阈值电压随着沟道长度的减少而增大.文章采用了一种简单模型解释了迁移率、阈值电压随着沟道长度的缩短而分别减少、增加的原因在于源漏接触电阻的影响.     

基于溶液法的金属诱导碟型晶畴多晶硅薄膜和薄膜晶体管的研究

以非晶硅为晶化前驱物,采用镍盐溶液浸沾的方法可以得到超大尺寸碟型晶畴结构的低温多晶硅薄膜.所得多晶硅薄膜的平均晶畴尺寸大约为50 μm,空穴的最高霍尔迁移率为30.8 cm~2/V·s,电子的最高霍尔迁移率为45.6 cm~2/V·s.用这种多晶硅薄膜为有源层,所得多晶硅TFT的场效应迁移率典型值为70～80 cm~2 /V·s,亚阈值斜摆幅为1.5 V/decade,开关电流比为1.01×10~7,开启电压为-8.3 V.另外,P型的TFT在高栅偏压和热载流子偏压下具有良好的器件稳定性.     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

Contact Resistance in Nanocrystalline Silicon Thin-Film Transistors

Thin-film transistors (TFTs) of nanocrystalline silicon (nc-Si:H) made by plasma-enhanced chemical vapor deposition have higher electron and hole field-effect mobilities than their amorphous counterparts. However, as the intrinsic carrier mobilities are raised, the effective carrier mobilities easily can become limited by the source/drain contact resistance. To evaluate the contact resistance, the nc-Si:H TFTs are made with a range of channel lengths. The TFTs are fabricated in a staggered top-gate bottom source/drain geometry. Both the intrinsic and the - or -doped nc-Si:H source/drain layers are deposited at 80-MHz excitation frequency at a substrate temperature of 150 . Transmission electron microscopy of the TFT cross section indicates that crystallites of doped nc-Si:H nucleate on top of the Cr source/drain contacts. As the film thickness increases, the crystallites coalesce, and the leaf-shaped crystal grains extend through the doped layer to the channel i layer. The contact resistance is estimated by measuring I_DS for several channel lengths at fixed gate and drain voltages. The results show that the contact resistance depends on the gate voltage and that the source/drain current of these TFTs at V_{DS =} 10 V becomes limited by the contact resistance when the channel length is less than 10 mum for n-channel and less than 25 mum for p-channel.