Internally biased transistor simulation model

An augmented transistor model where a three-terminal device is atomically biased internally is presented. A duplicate of the signal transistor is used to solve the bias equation. This model makes it convenient to compare circuit topologies by simulation     

Choosing a thermal model for electrothermal simulation of powersemiconductor devices

The literature proposes some thermal models needed for the electrothermal simulation of power electronic systems. This paper gives a useful analysis about the choice of the thermal model circuit networks, equivalent to a discretization of the heat equation by the finite difference method (FDM) and the finite-element method (FEM), and an analytic model developed by applying an internal approximation of the heat diffusion problem. The effect of the boundary condition representation and the introduced errors on temperature response at the heat source are studied. This study is advantageous, particularly for large surges of a short time duration     

A new electrothermal average model of the diode–transistor switch

In the paper a new electrothermal average model of the diode–transistor switch operating in any dc–dc converter is proposed. With the use of this model the non-isothermal characteristics of dc–dc converters in the steady-state can be obtained. The method of formulation of such a model and its structure are described in detail. The correctness of the elaborated model was verified by comparing the SPICE simulated characteristics of the buck and boost converters operating both in the continuous and discontinuous conducting mode, obtained by the electrothermal dc analysis with the proposed model and by the electrothermal transient analysis with the physical models of the diode and the transistor.     

Concise transient SPICE model for bipolar power transistor quasi-saturation simulation

A concise transient SPICE model is presented in this paper to predict both the static and the switching behaviour of power transistors, with emphasis placed on quasi-saturation effects. The model is proposed to simulate both ohmic and non-ohmic quasi-saturation phenomena by automatically adjusting the hole injection ratio term. The model incorporates the currently used Gummel-Poon (GP) model and an additional charge-control relation for the transistor's epitaxial collector. The turn-off charge removal phenomenon is not modelled specifically; however, the charge-control equation for the epitaxial collector region may partly simulate this effect where the quasi-saturation region is entered. The validity of the model is verified by comparison between the original SPICE bipolar junction transistor model and experimental data for both DC and turn-on conditions. Methods for determining the model parameters are described.     

Fast and accurate IGBT model for PSpice

A new PSpice IGBT model is presented which combines existing BJT and MOSFET models and equations to give a more realistic drain-gate capacitance model. Electrical simulation performance gives the accuracy of complex equation based models, but involves the computational time of simple inaccurate model based approaches. Simulation and experimental results vindicate the new model     

Multisim仿真软件中三极管模型参数的确定

Multisim仿真软件元件库中找不到特定型号三极管时,常常需要新建三极管模型并确定模型参数。从电流特性、输出特性等七个方面分析了三极管G-P模型参数的物理意义,并且通过实例说明了通常情况下三极管模型参数的估算方法。对于模型参数的准确性通过实验的方法加以验证,表明这种估算方法具有较好的仿真度和实用性。     

A computationally efficient model of single electron transistor for analog IC simulation

A compact analytical single electron transistor (SET) model is proposed. This model is based on the “orthodox theory” of single electron tunneling, valid for unlimited range of drain to source voltage, valid for single or multi-gate, symmetric or asymmetric devices and takes the background charge effect into account. This model is computationally efficient in comparison with existing models. SET characteristics produced by the proposed model have been verified against Monte Carlo simulator SIMON and show good agreement. This model has been implemented in HSPICE simulator through its Verilog-A interface to enable simulation with conventional MOS devices and single electron inverter has been simulated and verified with SIMON results. At high operating temperature, the thermionic current is taken into account.     

Two-dimensional simulation for resonant tunneling transistor

A new two-dimensional device simulation for the resonant tunneling transistor is presented. In the simulation, the one-dimensional Schrodinger equation is solved for the intrinsic area of the transistor and the conventional two-dimensional drift-diffusion equations are solved for the extrinsic part. Both equations are coupled with the carrier generation-recombination term in the drift-diffusion equations. In addition, the Poisson equation is also solved self-consistently with them to take the charge distribution effect into account. The two-dimensional simulator has been successfully applied to the analysis of a resonant tunneling transistor and it was found that the current-voltage characteristics sensitively depend on the base resistance. This means that a two-dimensional treatment of the voltage drop in the base region is essential for an accurate simulation     

High-frequency transistor modeling for circuit simulation

The typical S parameters for the HP35826E microwave transistor have been used to derive a transistor model which is suitable for use in circuit analysis programs. The RMS difference between the S parameters of the model and the transistor data is 0.33 dB and 3.3/spl deg/ for frequencies between 0.1 and 8 GHz and DC collector currents between 5 and 20 mA. It is shown that the inclusion of time delays at the collector and base of the transistor model greatly improves the accuracy of the transistor model. With the inclusion of the time delays in the transisting model, a one-section R-C ladder network can be used to model the behavior of the base-emitter junction up to frequencies of the order of 2f/SUB T/.     

An improved junction field-effect transistor static model forintegrated circuit simulation

A physics-based junction field-effect transistor (JFET) static model for integrated circuit simulation is developed. The model covers the behavior of the linear and saturation current regions without requiring fitting parameters. Subthreshold characteristics in the saturation region are also included in the model. Excellent agreement is obtained when the model is compared with experimental data     

PSpice high-frequency dynamic fluorescent lamp model

A new PSpice dynamic fluorescent lamp model based on high-frequency lamp characteristics is presented. The new model avoids the convergence problems found when using the Mader-Horn lamp model. A systematic approach is developed to derive the lamp model parameters from experimental data. Simulations are shown to agree closely with experimental data     

Avalanche multiplication in a compact bipolar transistor model forcircuit simulation

A simple weak avalanche model valid in a wide range of voltages and currents, is presented. The proposed model is derived by using the base-collector depletion capacitance for predicting the avalanche current. The model needs only one additional transistor parameter; the extraction method and temperature dependence of this parameter are discussed. The decrease in avalanche current for high collector current densities may originate from internal device heating, a voltage drop in the epilayer, or mobile carriers in the depleted part. From experimental results it is concluded that, below a critical hot-carrier current, the decrease in avalanche current due to mobile carriers is negligible     

The second breakdown in reverse biased transistor as an electrothermal switching

A thorough investigation has been given to second breakdown (SB) behaviors in transistors under reverse biased-base condition, and three types of behaviors have been shown: normal (without SB), and partial SB, as well as complete SB, which appear after very short delay times. The last two behaviors are shown to involve an electrothermal switching mechanism which operates at emitter collector voltages above the open base avalanche value VECO(a* > 1). Effects of local base punchthrough are shown which may also be important in some forward bias SB behaviors.     

功率PIN二极管PSpice子电路模型

提出一种改进的PIN二极管子电路模型。该模型能够反映PIN二极管的瞬态开关特性,将基区电导调制效应考虑在内。通过PSpice软件瞬态仿真PIN二极管的正向直流、反向恢复特性。利用该子电路对新型SiC材料PIN二极管建模仿真,仿真结果表明运用新材料对二极管开关性能有显著提高。     

Self consistent bipolar transistor models for computer simulation

Extended Ebers-Moll models of bipolar junction transistors have proven useful in computer-aided design packages for many years. The most recent refinement has been the incorporation of basewidth modulation or Early effect through a single model parameter called the Early voltage. This paper delineates the conditions under which a unique Early voltage can be defined and shows that a necessary condition is the base current must be independent of collector-base voltage. Further, a linearization of the large-signal model around a d.c. operating point leads to a small-signal hybrid-pi model in which the collector-base resistor r_u is necessarily absent. The absence of r_u has many implications in the design of high performance amplifier circuits.     

Circuit simulation models for the high electron mobility transistor

A three-terminal model is formulated for the high electron mobility transistor (HEMT) using charge-voltage relationships derived from the Boltzmann transport. Emphasis is placed on modeling the current transport of the two-dimensional electron gas (TEG) and the capacitance of the embedded parasitic MESFET structure. Furthermore, a distributed circuit topology is used to better model high-frequency effects, such as the transit time delay, in both small-signal and large-signal-transient analysis. The HEMT model is implemented in the circuit simulation program HP-SPICE. Both dc and ac simulation results are discussed.     

Lateral DMOS Power transistor design

Two dimensional analysis has been applied to model the lateral DMOST (LDMOST) transistor in the off condition. This approach predicts breakdown voltages beyond the conventional limit. Using this model, a 400 volt lateral transistor was designed, fabricated, and tested. The design values obtained from the numerical modeling, and the experimental results for a >425 volt LDMOST are presented.     

An approximate model for the graded-base transistor

The graded-base region of a conventional diffused-base transistor can be approximately modeled as two uniformly-doped regions, one heavily-doped near the surface and the other lightly-doped. This fundamental idea, combined with the Fletcher boundary conditions and the ambipolar approach, yields a one-dimensional analytical model for the graded-base transistor. For downward operation, this model—called the n⁺pp^?n⁺ transistor model—has only slight advantages as compared with existing analytical models such as the conventional uniform-base transistor model. For upward operation, the n⁺pp^?n⁺ transitor model has significant advantages.