Improved immunity to plasma damage in ultrathin nitrided oxides[CMOS technology]

Plasma-induced damage in various 3-nm thick gate oxides (i.e., pure O₂ and N₂O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as at the wafer edge for pMOS devices, while it occurs only at the wafer center for nWOS devices. These interesting observations could be explained by the polarity dependence of ultrathin oxides in charge-to-breakdown measurements. Additionally, ultrathin N₂O-nitrided oxides show superior immunity to charging damage, especially for pMOS devices     

Plasma-induced charging damage in ultrathin (3-nm) gate oxides

Plasma-induced damage in various 3-nm-thick gate oxides (i.e., pure oxides and N₂O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Both charge-to-breakdown and gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as the wafer edge for pMOS devices, while only at the wafer center for nMOS devices. These interesting observations could be explained by the strong polarity dependence of ultra thin oxides in charge-to-breakdown measurements of nMOS devices. In addition, pMOS devices were found to be more susceptible to charging damage, which can be attributed to the intrinsic polarity dependence in tunneling current between nand p-MOSFETs. More importantly, our experimental results demonstrated that stress-induced leakage current (SILC) caused by plasma damage can be significantly suppressed in N₂O-nitrided oxides, compared to pure oxides, especially for pMOS devices. Finally, nitrided oxides were also found to be more robust when subjected to high temperature stressing. Therefore, nitrided oxides appear to be very promising for reducing plasma charging damage in future ULSI technologies employing ultrathin gate oxides     

Monitoring plasma-process induced damage in thin oxide

Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the `antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken     

Oxide thickness dependence of plasma charging damage

Charging damage induced in oxides with thickness ranging from 8.7 to 2.5 nm is investigated. Results of charge-to-breakdown (Q_bd) measurements performed on control devices indicate that the polarity dependence increases with decreasing oxide thickness at both room and elevated temperature (180°C) conditions. As the oxide thickness is thinned down below 3 nm, the Q_bd becomes very sensitive to the stressing current density and temperature. Experimental results show that severe antenna effect would occur during plasma ashing treatment in devices with gate oxides as thin as 2.6 nm. It is concluded that high stressing current level, negative plasma charging, and high process temperature are key factors responsible for the damage.     

Nondestructive DCIV method to evaluate plasma charging damage inultrathin gate oxides

Understanding and minimizing plasma charging damage to ultrathin gate oxides became a growing concern during the fabrication of deep submicron MOS devices. Reliable detecting techniques are essential to understand its impact on device reliability. As the gate oxide thickness of MOSTs rapidly scales down, the conventional nondestructive methods such as capacitor C-V and threshold voltage and subthreshold swing of MOSTs are no longer effective for evaluating this damage in gate oxide. In this paper, the newly developed direct-current current-voltage (DCIV) technique is reported as an effective monitor for plasma charging damage in ultrathin oxide. The DCIV measurements for p-MOSTs with both 50- and 37-Å gate oxides clearly show the plasma charging damage region on the wafers and are consistent with the results of charge-to-breakdown measurements. In comparing with charge-to-breakdown measurement and other conventional methods, the DCIV technique hits the advantages of nondestructiveness, high sensitivity and rapid evaluation     

Evaluation of plasma charging damage in ultrathin gate oxides

Monitoring of plasma charging damage in ultrathin oxides (e.g., <4 mm) is essential to understand its impact on device reliability. However, it is observed that the shift of several device parameters, including threshold voltage, transconductance, and subthreshold swing, are not sensitive to plasma charging and thus not suitable for this purpose. Consequently, some destructive methods, such as the charge-to-breakdown measurement, are necessary to evaluate plasma damage in the ultrathin oxides     

Preventing dielectric damage of low-k organic siloxane by passivation treatment

An organic SOG, the Hybird-Organic-Siloxane-Polymer (HOSP), has high applicability to ULSI processes, because of the low dielectric constant of about 2.5. However, the HOSP film will be damaged after photoresist removal. The function groups of HOSP will be destroyed by O₂ plasma ashing and chemical wet stripper, which leads to electrical degradation. In order to avoid the issue, H₂ plasma treatment is proposed to prevent HOSP film from photoresisit stripping damage. It is found that leakage current is decreased significantly and the dielectric constant is still maintained at a low k value even after photoresist stripping. Therefore, H₂ plasma treatment is an effective technique to enhance the resistance of HOSP film against photoresist stripping damage.     

Dependence of plasma-induced oxide charging current on Al antennageometry

The dependence of the plasma-induced oxide charging current on Al electrode geometry has been studied. The stress current is collected only through the electrode surfaces not covered by the photoresist during plasma processes and therefore is proportional to the edge length of the electrode during etching and proportional to the electrode area during photoresist ashing. Knowing the measured oxide charging currents, one should be able to predict the impact of these processes on oxide integrity and interface stability for a given antenna geometry more accurately     

各膜层对光刻胶灰化的影响

研究各膜层对灰化速率的影响,增强对灰化工艺的了解,为四次光刻工艺改善提供参考。采用探针台阶仪测量在相同灰化条件下不同膜层样品的灰化速率和有源层损失量,对结果进行机理分析和讨论。实验结果表明:有源层会降低灰化速率,源/漏金属层可以增大灰化速率,栅极金属层对灰化速率无影响。对于正常膜层结构的阵列基板,源/漏层图形密度越大,灰化速率越小,图形密度每增大1%,灰化速率下降14nm/min。有源层和源/漏金属层对灰化等离子体产生影响,从而影响灰化速率。     

Modeling of oxide breakdown from gate charging during resist ashing

Plasma damage was observed after exposing an antenna capacitor structure to an O₂ plasma in a single wafer resist asher. The observed early breakdown is well modeled by surface charging caused by plasma nonuniformity. Here, the plasma nonuniformity was induced by gas flow and electrode configuration. The present results agree well with our previous results where magnetic field leads to a nonuniform plasma. In this model, nonuniformity leads to a local imbalance of ion and electron currents which charge up the gate surface and degrade the gate oxide. Using SPICE, a circuit model for the test structure and plasma measurements, the Fowler-Nordheim current through the thin oxide regions at different points on the wafer was calculated and found to agree well with the observed damage. The important implication of this work on oxide reliability is that the modeling gives a clear picture to this breakdown mechanism. The charging model can also be applied to any ashing process in any nonuniform plasma. Moreover, this model provides a physical basis for design rules of device structures for the fabrication of reliable gate oxides in submicron MOS technology     

FGA effects on plasma-induced damage: beyond the appearances

Indispensable for manufacturing of modern CMOS technologies, plasma processes result in charging of dielectric surfaces, thus damaging the gate oxide. A forming gas annealing (FGA) step is usually done at the end of the process to passivate and/or recover this damage. We investigated this problem on thin (3.5 nm) gate oxides by using a series of stress-anneal-stress steps on devices with different level of latent damage. Our results confirm that FGA actually reduces the number of traps responsible for stress-induced leakage current (SILC) or for microbreakdown in ultrathin gate oxides, but also put in evidence that defects induced by plasma treatments and those generated by way of electrical stress feature different anneal kinetics. Further, we have identified two categories of dielectric breakdown events, whose characteristics are strongly modified by the FGA step.     

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Low-damage hard-mask (HM) plasma-etching technology for porous SiOCH film (k=2.6) has been developed for robust 65-nm-node Cu dual damascene interconnects (DDIs). No damage is introduced by fluorocarbon plasma etching irrespective of whether rigid (k=2.9) or porous (k=2.6) SiOCH films are used, due to the protective CF-polymer layer deposited on the etched sidewall. The etching selectivity of the SiOCH films to the inorganic HMs is kept high by controlling the radical ratio of carbon relative to oxygen in the etching plasma gas. However, oxidation damage penetrates the films from the sidewalls due to the O₂ plasma used for photoresist ashing. This damage is increased by the porous structure. As a result, we developed a via-first multi-hard-mask process for the DD structure in porous SiOCH film with no exposure to O ₂-ashing plasma, and we controlled the via-taper angle by RF bias during etching. We fabricated robust Cu DDIs with tapered vias in porous SiOCH film that can be applied to 65-nm-node ULSIs and beyond     

Removal of post-etch photoresist and sidewall residues using organic solvent and additive combined with physical forces

The effect of tetramethyl ammonium hydroxide (TMAH) used as additive in organic solvent (N-methyl pyrrolidone, NMP) on removal efficiency of post-etch photoresist was investigated on both blanket substrate and single damascene structures. In contrast to plasma ashing, photoresist removal using NMP/TMAH combined with megasonics showed no carbon depletion and no significant change in k-value. Mixing TMAH with NMP enhanced photoresist removal efficiency with respect to pure NMP. Photoresist removal using NMP/TMAH resulted in lower low-k capacitance (lower k-value) compared with that of plasma ashing process, due to the removal of the damaged layer generated during plasma etching. As a consequence of the removal of the damaged layer, a CD change was observed. The CD loss was estimated to be about 7 nm for 1% TMAH, and became negligible for 0.1% TMAH. Analysis of low-k sidewall using angle-resolved X-ray photoelectron spectroscopy showed that solvent mixture containing TMAH also removed sidewall residues generated by the etch plasma.     

Novel Single-Wafer Single-Chamber Dry and Wet Hybrid System for Stripping and In Situ Cleaning of High-Dose Ion-Implanted Photoresists

There is increasing demand for moving from batch immersion tools to single-wafer spin tools for silicon wafer cleaning, etching, and photoresist/residue removal in advanced semiconductor manufacturing. However, high-dodse ion-implanted photoresist removal using a conventional single-wafer spin tool is very difficult. We have developed a novel single-wafer single-chamber dry and wet hybrid system in combination with dry ashing and moderate-temperature wet-cleaning treatments by implementing an atmospheric-pressure plasma unit into a conventional single-wafer spin cleaning tool. This compact single-wafer single-chamber system can completely remove the hardened photoresist due to high-dose ion-implantation by an atmospheric-pressure plasma ashing process followed by an in situ wet chemical process in the same single chamber within 2 min. This single-wafer single-chamber dry/wet hybrid system offers less than 1/3 smaller footprint, less than 1/4 shorter cycle time (for 50 wafer processing), and potentially better process control and less contamination risk, as well as lower equipment cost, compared to the conventional combination of two separate dry- and wet-processing systems.      

Effects of plasma charging damage on the noise performance ofthin-oxide MOSFET's

The effects of plasma charging damage on the noise properties of MOSFET's which is a necessary consideration for high-performance analog applications were studied using 1/f noise, Random Telegraph Signal (RTS) noise and charge pumping techniques. Plasma ashing significantly increases the drain flicker noise, more with larger antenna sizes, mainly in the low-frequency and low-gate-bias regime. The observed RTS reveals that an oxide trap with a few milliseconds time constant was induced by the plasma processing. This oxide trap is located in the energy space which corresponds to the low gate bias of device. This trap may be reproduced by Fowler Nordheim stress as suggested by noise and charge pumping measurements, supporting the notion that plasma ashing damage is a result of electrical stress, not radiation, for example     

Effects of wafer temperature on plasma charging induced damage toMOS gate oxide

The effect of wafer temperature on damage to thin MOS gate oxide from plasma has been investigated for the first time. As the wafer surface temperature during an O₂ plasma exposure increases from 145°C to 340°C, the damage measured from charge-to-breakdown (Q_bd) increases dramatically. This result agrees with Fowler-Nordheim tunneling current mechanism for plasma charging and the temperature activated damage model. The increase of damage at higher wafer processing temperature indicates that elevated temperature plasma processes, such as plasma enhanced CVD and Cu etching, can be expected to be more susceptible to charging damage than low temperature plasma processes     

Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation

It is shown that the primary manifestation of charging damage in thin (<4 nm) oxides is a degradation of dielectric integrity, while the primary manifestation of damage in thick (>6 nm) oxides is a shift in threshold voltage and/or the degradation of hot-carrier immunity. It is therefore necessary to monitor both dielectric integrity and parametric shifts to determine the consequences of charging damage on a technology with multiple gate oxide thicknesses. We demonstrate the efficacy of a ramp breakdown methodology for measuring dielectric integrity, showing that a simple measurement of current is not sufficiently sensitive, and that results equivalent to a lengthy time-to-breakdown test may be achieved. We describe a highly accelerated hot-carrier stress for monitoring damage on thicker oxide and show how it illuminates latent damage and is superior to Fowler–Nordheim stressing for this purpose. Furthermore, we show data on some thousands of chips from a manufacturing line, which demonstrates robust charging behavior for realistic gate and wiring antennas.     

超薄氧化门的等离子体充电损伤机理

探讨了金属氧化物半导体场效应管超薄氧化门在等离子体加工中造成的充电损伤机理,应用碰撞电离模型解释了超薄氧化门对充电损伤比厚氧化门具有更强免疫力的原因.     

Plasma charging damage on ultrathin gate oxides

Capacitor C-V and threshold voltage and subthreshold swing of MOSFET's with gate oxide thickness varying from 2.2 to 7.7 nm are analyzed to study the plasma charging damage by the metal etching process. Surprisingly, the ultrathin gate oxide has better immunity to plasma charging damage than the thicker oxide, thanks to the excellent tolerance of the thin gate oxide to tunneling current. This finding has very positive implications for the prospect of manufacturable scaling of gate oxide to very thin thickness     

A comparison between plasma charging-damage and inductive-damage: Damage response to Fowler-Nordheim stress

This paper reports on the results of a study performed to compare the effects of charging damage and inductive damage to 0.5 μm n-channel MOSFETs arising from plasma etching at the gate-definition etch and metal-1 etch levels, respectively. The MOSFETs were fabricated on 200 mm p/p+ silicon wafers using a full CMOS process. The gate-definition etch step was performed using a chlorine-based chemistry and the metal etch step was done using a BCl₃/N₂/Cl₂ plasma. It is found that charging damage is electrically inactive after the full CMOS process flow; however, it is electrically activated by Fowler-Nordheim (F-N) stress when charging damage is clearly seen to correlate with the area of charging antenna in the device. Inductive damage, on the other hand, is seen to impact transistor parameters directly after the CMOS process and before the application of F-N stress. This is attributed to distinctly different mechanisms that are responsible for the creation of the two types of damage: charging damage arises from a dc current stress, whereas inductive damage is suggested to arise from ac current stress.