Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Using a fluorinated high-k/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-k deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-fc is a concern. The novel fluorinated Ta_infinC_y/HfZrO_infin/SRPO gate stack device exceeds the positive-bias-temperature-instability and negative-bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon.     

Negative Bias Temperature Instability Dominated Degradation of Metal-Induced Laterally Crystallized p-Type Polycrystalline Silicon Thin-Film Transistors

Device degradation of solution-based metal-induced laterally crystallized p-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is studied under dc bias stresses. While typical negative bias temperature instability (NBTI) or electron injection (EI) is observed under $-V_{g}$ or $-V_{d}$ only stress, respectively, no typical hot carrier (HC) degradation can be identified under high $-V_{d}$ stress combined with either low or high $-V_{g}$ stress. Instead, mixed NBTI and EI degradation is observed under combined low $-V_{g}$ and $-V_{d}$ stresses; and combined degradation of NBTI and HC occurs under high $-V_{d}$ and moderate $-V_{g}$ stresses. NBTI is the dominant mechanism in both cases. Grain boundary (GB) trap generation is found to correlate with the NBTI degradation with the same time exponent, suggesting the key role of GB trap generation in poly-Si TFTs' degradation.      

Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses

Device degradation behaviors of typical-sized n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors were investigated in detail under two kinds of dc bias stresses: hot-carrier (HC) stress and self-heating (SH) stress. Under HC stress, device degradation is the consequence of HC induced defect generation locally at the drain side. Under a unified model that postulates, the establishment of a potential barrier at the drain side due to carrier transport near trap states, device degradation behavior such as asymmetric on current recovery and threshold voltage degradation can be understood. Under SH stress, a general degradation in subthreshold characteristic was observed. Device degradation is the consequence of deep state generation along the entire channel. Device degradation behaviors were compared in low V_d-stress and in high V_d-stress condition. Defect generation distribution along the channel appears to be different in two cases. In both cases of SH degradation, asymmetric on current recovery was observed. This observation, when in low V_d-stress condition, is tentatively explained by dehydrogenation (hydrogenation) effect at the drain (source) side during stress     

金属单向诱导横向晶化激光修饰多晶硅薄膜晶体管

对采用金属诱导单一方向横向晶化(metal induced unilaterally crystallization,MIUC)并结合激光后退火技术,以提高多晶硅薄膜晶体管的性能,进行了深入研究.MIUC薄膜晶体管已具有良好的器件性能和均匀性,再加以三倍频YAG激光退火后的MIUC薄膜晶体管,其场效应迁移率则可提高近一倍.器件的多种性能和参数的均匀性与所用修饰性的激光处理条件密切相关,具有规律性,故而是可控的,这为工业化技术的掌控提供了基础.     

High-Performance Nanowire TFTs With Metal-Induced Lateral Crystallized Poly-Si Channels

High-performance poly-Si thin-film transistors (TFTs) with 50-nm nanowire (NW) channels fabricated by integrating a simple spacer formation scheme and metal-induced-lateral-crystallization (MILC) technique are proposed. By using the sidewall spacer formation scheme, the NW channels with nanometer-scale feature sizes can be easily fabricated, exhibiting superior channel controllability through the triple-gate structure. In employing the MILC technique, the grain crystallinity of NW channels is significantly superior to that formed by the solid-phase-crystallization (SPC) technique. Therefore, the MILC NW TFT exhibits greatly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, and higher field-effect mobility, as compared to those of the SPC NW TFT. Moreover, the superior threshold-voltage rolloff characteristics of MILC NW TFT are also demonstrated.     

Dynamic Bias Instability of p-Channel Polycrystalline-Silicon Thin-Film Transistors Induced by Impact Ionization

The dynamic stress switching of p-channel polycrystalline-silicon (poly-Si) thin-film transistors from full depletion to accumulation bias creates the high electric field near source/drain (S/D) junctions due to the slow formation of the accumulated electrons at the $hbox{SiO}_{2}/hbox{poly}$ -Si interface. The high electric field causes impact ionization near the S/D, where the secondary electrons surmount the $hbox{SiO}_{2}$ barrier and are trapped near the interface. The channel region near the S/D is inverted to p-type by the trapped electrons, and the effective channel length is reduced. The drain current increases with the stress time, particularly for short-channel devices.      

The Influence of Channel Compositions on the Electrical Properties of Solution-Processed Indium-Zinc Oxide Thin-Film Transistors

Electrical properties of indium-zinc oxide (IZO) thin-film-transistors (TFTs) based on solution processes with various channel compositions are investigated in this paper. Amorphous IZO thin films with high transparency and smooth/uniform surfaces are deposited by spin-coating. The In:Zn ratio is varied by adjusting the precursor compositions, and its influences on the electrical properties, such as resistivity, mobility, and threshold voltage, etc., of IZO films and TFTs are studied. The devices showed field effect mobility ranging from 0.07 to 2.13 ${hbox{cm}}^{2}/{hbox{V}}cdot{hbox{s}}$ with the In component $({hbox{In}}/({hbox{In}}+{hbox{Zn}}))$ varying from 0.2 to 0.5.      

Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors

This paper is focused on the stability of n-channel laser-crystallized polysilicon thin-film transistors (TFTs) submitted to a hydrogenation process during the fabrication and with small grains dimension. With the aid of numerical simulations, we investigate the effects of static stress using two types of procedures: the on stress and the hot carrier stress. Results show that the variations of trap state density into the whole polysilicon layer and not only near the drain junction are responsible for the degradation of TFTs performances in both the two types of stress and that the interface trap states play a negligible role compared to the bulk trap states     

Electrical Instability of RF Sputter Amorphous In-Ga-Zn-O Thin-Film Transistors

Bias-temperature-stress (BTS) induced electrical instability of the RF sputter amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) was investigated. Both positive and negative BTS were applied and found to primarily cause a positive and negative voltage shift in transfer $(I _{rm DS} -V _{rm GS})$ characteristics, respectively. The time evolution of bulk-state density $(N _{rm BS})$ and characteristic temperature of the conduction-band-tail-states $(T _{G})$ are extracted. Since both values showed only minor changes after BTS, the results imply that observed shift in TFT $I _{rm DS} -V _{rm GS}$ curves were primarily due to channel charge injection/trapping rather than defect states creation. We also demonstrated the validity of using stretch-exponential equation to model both positive and negative BTS induced threshold voltage shift $(Delta V _{rm th})$ of the a-IGZO TFTs. Stress voltage and temperature dependence of $Delta V _{rm th}$ evolution are described.      

Improved Uniformity and Electrical Performance of Continuous-Wave Laser-Crystallized TFTs Using Metal-Induced Laterally Crystallized Si Film

Continuous-wave (CW) laser crystallization (CLC) of amorphous Si (α-Si) has previously been employed to fabricate high-performance low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Unfortunately, their uniformity was poor because the shape of the beam profiles was Gaussian. In this study, α-Si film was replaced by Ni-metal-induced laterally crystallized Si (MILC-Si). MILCLC-Si was MILC-Si irradiated by a CW laser (λ ≈ 532 nm and power ≈ 3.8 W). It was found that the performance and uniformity of the metal-induced laterally crystallized continuous-wave laser crystallization - thin film transistors (MILCLC-TFTs) were much better than those of the CLC-TFTs. Therefore, the MILCLC-TFT is suitable for application in systems on panels.     

绝缘层/有源层界面修饰及对有机薄膜晶体管性能的影响

制备了具有修饰层的有机薄膜场效应晶体管,采用高掺杂Si作为栅极,传统的无机绝缘材料SiO2作为栅绝缘层,有机绝缘材料PMMA或OTS作为修饰层,CuPc作为有源层,Au作为源、漏极.测试结果表明,采用经过修饰的栅绝缘层SiO2/OTS和SiO2/PMMA的两种器件的开关电流比最高可达8×104,迁移率最高为1.22×10-3cm2/(V·s),而漏电流仅为10-10A,总体性能优于单层SiO2器件.     

绝缘层/有源层界面修饰及对有机薄膜晶体管性能的影响

制备了具有修饰层的有机薄膜场效应晶体管,采用高掺杂Si作为栅极,传统的无机绝缘材料SiO2作为栅绝缘层,有机绝缘材料PMMA或OTS作为修饰层,CuPc作为有源层,Au作为源、漏极.测试结果表明,采用经过修饰的栅绝缘层SiO2/OTS和SiO2/PMMA的两种器件的开关电流比最高可达8×104,迁移率最高为1.22×10-3cm2/(V·s),而漏电流仅为10-10A,总体性能优于单层SiO2器件.     

Advanced Amorphous Silicon Thin-Film Transistors for AM-OLEDs: Electrical Performance and Stability

We fabricated and characterized the advanced amorphous silicon thin-film transistors with a bilayer structure for both the active and gate dielectric films. The electrical field across the gate insulator has a significant influence on the device threshold voltage electrical stability. We show that high thin-film transistor stability can be achieved even under the presence of a high channel current. Its electrical and high-temperature stability improves up to a factor of five when the TFT biasing condition changes from the linear to the saturation region of operation.     

Electrical Properties of Surface-Tailored ZnO Nanowire Field-Effect Transistors

A review on the tunable electrical properties of ZnO nanowire field-effect transistors (FETs) is presented. The FETs made from surface-tailored ZnO nanowire exhibit two different types of operation modes, which are distinguished as depletion and enhancement modes in terms of the polarity of the threshold voltage. We demonstrate that the transport properties of ZnO nanowire FETs are associated with the influence of nanowire size and surface roughness associated with the presence of surface trap states at the interfaces as well as the surface chemistry in environments.      

Radio-Frequency Operation of Transparent Nanowire Thin-Film Transistors

In this letter, radio-frequency characterization of fully transparent thin-film transistors (TFTs) based on chemically synthesized nanowires (NWs) has been carried out. The NW TFTs show current-gain cutoff frequency $f_{T}$ of 109 MHz and power-gain cutoff frequency $f_{max}$ of 286 MHz. The TFTs were fabricated on glass substrates using aligned $hbox{SnO}_{2}$ NWs as the transistor channel and sputtered indium–tin–oxide films as the source–drain and gate electrodes. Besides exhibiting $≫$ 100-MHz operation frequencies, the transparent NW TFTs show a narrow distribution of performance metrics among different devices. These results suggest the NW-TFT approach may be promising for high-speed transparent and flexible integrated circuits fabricated on diverse substrates.      

L-MBE法制备以ZnO为沟道层的薄膜晶体管

采用激光分子束外延法(L-MBE)在SiNx/Si(111)衬底上制备了高质量的ZnO薄膜,用X射线衍射(XRD)和原子力显微镜(AFM)对薄膜的晶体结构、表面形貌进行了表征,结果表明ZnO薄膜有高度的c轴择优取向,薄膜表面平整致密.并以ZnO薄膜为沟道层制作了薄膜晶体管(ZnO-TFT),该晶体管工作在n沟道增强模式,阈值电压为17.5V,电子的场迁移率达到1.05cm2/(V·s).     

L-MBE法制备以ZnO为沟道层的薄膜晶体管

采用激光分子束外延法(L-MBE)在SiNx/Si(111)衬底上制备了高质量的ZnO薄膜,用X射线衍射(XRD)和原子力显微镜(AFM)对薄膜的晶体结构、表面形貌进行了表征,结果表明ZnO薄膜有高度的c轴择优取向,薄膜表面平整致密.并以ZnO薄膜为沟道层制作了薄膜晶体管(ZnO-TFT),该晶体管工作在n沟道增强模式,阈值电压为17.5V,电子的场迁移率达到1.05cm2/(V·s).     

Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors

Constant-voltage-bias (V_DS = V_GS = 30 V) stress measurements are performed for a period of 10⁵ s on thin-film transistors (TFTs) with amorphous indium-gallium-zinc-oxide (IGZO) channel layers fabricated via RF sputtering using a postdeposition annealing temperature of 200degC, 250degC, or 300degC. Thermal silicon dioxide is employed as a TFT bottom-gate insulator. All SiO₂/IGZO TFTs tested exhibit the following: 1) a positive rigid log(I_D)- V_GS transfer curve shift; 2) a continuous drain-current decrease over the entire stress duration; and 3) recovery of the log(I_D)-V_GS transfer curve toward the prestressed state when the stressed TFT is left unbiased in the dark at room temperature for an extended period of time. The SiO₂/IGZO TFTs subjected to a higher postdeposition annealing temperature are more stable. A small (and typically negligible) amount of clockwise hysteresis is present in the log(I_D) -V_GS transfer curves of IGZO TFTs. These instability and hysteresis observations are consistent with a SiO₂/ IGZO TFT instability mechanism involving electron trapping within the IGZO channel layer.     

Characteristics of Gate-All-Around Twin Poly-Si Nanowire Thin-Film Transistors

We have investigated the characteristics of gate-all-around (GAA) twin polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs). The NW channel and surrounding gate imparted the GAA twin NW TFT with superior channel controllability. Moreover, the combination of the high surface-to-volume ratio of the NW and the split channel structure led to highly efficient $hbox{NH}_{3}$ plasma treatment, which reduced the effective grain-boundary trap-state density. The GAA twin NW TFT exhibited greatly improved electrical performance, including a lower threshold voltage, a steeper subthreshold swing (114 mV/dec), a higher on/off current ratio $(≫! hbox{10}^{8})$, and a virtual absence of drain-induced barrier lowering (13 mV/V).