Password Authentication Using Hopfield Neural Networks

Password authentication is a common approach to system security. The conventional verification table approach has significant drawbacks. Recently, neural networks have been used for password authentication to overcome the shortcomings of traditional approaches. In neural network approaches to password authentication, no verification table is needed; rather, encrypted neural network weights are stored within the system. Existing layered neural network techniques have their limitations such as long training time and recall approximation. This study proposes the use of a Hopfield neural network technique for password authentication. In comparison to existing layered neural network techniques, the proposed method provides better accuracy and quicker response time to registration and password changes.     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Fast algorithms for selection of test nodes of an analog circuit using a generalized fault dictionary approach

Selection of test nodes is an important phase of the fault dictionary approach. It is demonstrated in this paper that the techniques used for this purpose in other approaches of analog fault diagnosis like fault analysis and fault verification are not in general suitable for the fault dictionary approach. The ambiguity set is a simple and effective concept for choosing test nodes in the context of dictionaries. These sets are formed such that each faulty condition lies in only one ambiguity set. Deviating from this thinking, overlapping ambiguity sets are proposed in this paper, giving rise to a generalized fault dictionary. These sets use information more fully and hence reduce the number of test nodes. The concept of hashing is applied in this paper for selecting test nodes. This gives a linear time algorithm (linear in the number of fault voltage specificationsf) and it isf times faster than the existing methods. It is not possible to select test nodes faster than this. This technique can also be used to select test nodes by the process of elimination of nodes. This is also linear inf per node elimination. Even a group of nodes can be eliminated or selected within the same computation. This freedom is not possible with the existing methods.     

模拟电路k故障诊断理论的数学模型

故障诊断理论是模拟电路故障诊断理论的一个重要分支。现已提出的k故障诊断方法有支路法、节点法、割集法、回路法以及网孔法,这些方法都能较好地完成故障定位与故障定值,并在可测性设计方面有了较大的发展,但是这些方法还没有一个统一的理论模型。本文对这几种方法进行了总结和概括,提出了k故障诊断理论的统一数学模型,这项研究工作的目的是为了加强k故障诊断理论的系统性和严密性,并为更深入的研究和实践提供了理论依据。     

A design for testability approach for nano-CMOS analogue integrated circuits

Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal–oxide–semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker.     

模拟电路软故障诊断的研究

分析了模拟电路软故障诊断的重要性及现有的各种软故障诊断方法。对模拟电路软故障诊断字典法中基于支路屏蔽原理、电路参数随元件参数变化轨迹、节点电压灵敏度序列守恒定理和节点电压增量关系方程的四个研究方向各自的基本原理和优缺点进行了探讨;介绍了基于神经网络,结合模糊理论、小波变换的现代模拟电路软故障诊断的两个方向的研究现状;同时从通用的软故障诊断方法、大规模模拟电路的诊断策略和数模混合集成电路的诊断需求三方面指出了模拟电路软故障诊断的发展趋势和亟待解决的问题。     

Fault Diagnosis of Analog Circuits Using Systematic Tests Based on Data Fusion

An analog fault diagnosis approach using a systematic step-by-step test is proposed for fault detection and location in analog circuits with component tolerance and limited accessible nodes. First, by considering soft faults and component tolerance, statistics-based fault detection criteria are established to determine whether a circuit is faulty by measuring accessible node voltages. For a faulty circuit, fuzzy fault verification is performed using the accessible node voltages. Furthermore, using an approximation technique, the most likely faulty elements are identified with a limited number of circuit gain measurements at selected frequencies. Finally, employing the D-S evidence theory, synthetic decision is made to locate faults according to the results of fault verification and estimation. Unlike other methods which use a single diagnosis method or a particular type of measurement information, the proposed approach makes use of the redundancy of different types of measurement information and the combined use of different diagnosis methods so as to improve diagnosis accuracy.     

故障诊断交流字典法的前向神经网络实现方法

提出了一种采用ＢＰ算法的前向多层神经网络实现模拟电路故障诊断交流字典的方法。     

Single-Link Failure Detection in All-Optical Networks Using Monitoring Cycles and Paths

In this paper, we consider the problem of fault localization in all-optical networks. We introduce the concept of monitoring cycles (MCs) and monitoring paths (MPs) for unique identification of single-link failures. MCs and MPs are required to pass through one or more monitoring locations. They are constructed such that any single-link failure results in the failure of a unique combination of MCs and MPs that pass through the monitoring location(s). For a network with only one monitoring location, we prove that three-edge connectivity is a necessary and sufficient condition for constructing MCs that uniquely identify any single-link failure in the network. For this case, we formulate the problem of constructing MCs as an integer linear program (ILP). We also develop heuristic approaches for constructing MCs in the presence of one or more monitoring locations. For an arbitrary network (not necessarily three-edge connected), we describe a fault localization technique that uses both MPs and MCs and that employs multiple monitoring locations. We also provide a linear-time algorithm to compute the minimum number of required monitoring locations. Through extensive simulations, we demonstrate the effectiveness of the proposed monitoring technique.      

Fault Diagnosis in Mixed-Signal Low Testability System

This paper describes a new approach for fault diagnosis of analog multi-phenomenon systems with low testability. The developed algorithms include identification of ambiguity groups, fault diagnosis methodology and solving low testability equations. Our aim is to identify a minimum number of faulty parameters that satisfy the test equations called a minimum form solution. An algorithm to find a minimum form solution is presented, which is based on the solution invariant matrix and an identification of singular cofactors of this matrix. System simulation using a developed C++ and Matlab programs was performed to test different faulty circuits. Test examples are discussed and simulation results are presented.     

测试性技术分析与试验验证刍议

测试性质量特性是武器装备试验考核内容之一,攸关武器装备能否快速地检测故障并隔离故障。文中阐述了装备测试技术设计、测试性试验需求和靶场验证方法,着重研究了测试性定性检查、定量检查的基本准则和实施途径。并指出故障特征的分析提取和样本集的有效生成是测试验证的关键,旨在为提升武器装备测试性试验能力提供参考。     

网络诊断研究

本文提出了多种新的故障定值和定位方法,系统地阐述了网络诊断理论,以及网络诊断与网络分析和网络综合之间的关系.     

A Novel Test Point Selection Method for Analog Fault Dictionary Techniques

Most of the recently reported test point selection algorithms for analog fault dictionary techniques are based on integer-coded table (ICT) technique. Hence, the accuracy of these algorithms is closely related to the accuracy of the ICT technique. Unfortunately, this technique is not accurate, especially when the size of fault dictionary is large. This paper proposes an accurate fault-pair Boolean table technique for the test point selection problem. First, the approach to transform the fault dictionary into a fault-pair Boolean table is introduced. Then, a test point selection algorithm based on the fault-pair Boolean table is proposed. Thirdly, several example circuits are used to illustrate the proposed algorithm. Simulated results indicate that the proposed method is more accurate than the other methods. Therefore, it is a good solution for minimizing the size of the test point set.     

Design for Testability Techniques at the Behavioral and Register-Transfer Levels

Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.     

Analogue electronic circuit diagnosis based on ANNs

Feed-forward artificial neural networks (ANNs) have been applied to the diagnosis of nonlinear dynamic analogue electronic circuits. Using the simulation-before-test (SBT) approach, a fault dictionary was first created containing responses observed at all inputs and outputs of the circuit. The ANN was considered as an approximation algorithm to capture mapping enclosed within the fault dictionary and, in addition, as an algorithm for searching the fault dictionary in the diagnostic phase. In the example given DC and small signal frequency domain measurements were taken as these data are usually given in device’s data-sheets. A reduced set of data per fault (DC output values, the nominal gain and the 3 dB cut-off frequency, measured at one output terminal) was recorded. Soft (parametric) and catastrophic (shorts and opens) defects were introduced and diagnosed simultaneously and successfully. Large representative set of faults was considered, i.e., all possible catastrophic transistor faults and qualified representatives of soft transistor faults were diagnosed in an integrated circuit. The generalization property of the ANNs was exploited to handle noisy measurement signals.     

具有容差的模拟电路故障定位的神经网络实现

结合Ｋ故障诊断和ＢＰ网络的分类功能,提出了一种神经网络实现模拟故障定位的方法,该方法将ＢＰ网络训练成具有推广能力的广义故障字典。     

An Efficient Dictionary Organization for Maximum Diagnosis

The major problem of fault diagnosis with a fault dictionary is the enormous amount of data. The technique used to manage this data can have a significant effect on the outcome of the fault diagnosis procedure. If information is removed from a fault dictionary in order to reduce the size of the dictionary, its ability to diagnose stuck-at faults and unmodeled faults may be severely debased. Therefore, we focus on methods for producing a dictionary that is both small and lossless-compacted. We propose an efficient dictionary for maximum diagnosis, which is called SD-Dictionary. This dictionary consists of a static sub-dictionary and a dynamic sub-dictionary in order to make a smaller dictionary while maintaining the critical information needed for the diagnostic ability. Experimental results on ISCAS’ 85, ISCAS’ 89 and ITC’ 99 benchmark circuits show that the size of the proposed dictionary is substantially reduced, while the dictionary retains most or all of the diagnostic capability of the full dictionary. This work was supported by the “System IC 2010” project of Korea Ministry of Science and Technology and Ministry of Commerce, Industry and Energy. Editor: Y. Takamatsu Sunghoon Chun received the B.S. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea, in 2002. He was a Reseach Engineer with ASIC Research Center in Yonsei University. He researched for test methodologies for SoC. He received the M.S. degrees in Electrical and Electronic Engineering from Yonsei University in 2005. He is currently working toward Ph.D. degree in Electrical and Electronic Engineering at Yonsei University. His area of interests includes SoC testing, delay testing, fault diagnosis, functional testing for processor based system and test methodologies for signal integrity faults. Sangwook Kim received the B.S., and M.S. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea, in 1999, and 2001, respectively. He researched for Digital Signal Processor design and fault diagnosis of VLSI. He is a Research Engineer with SoC Design Group of System IC Division in LG Electronics, Inc. He is currently interested in SoC design for HDTV and design verification. Hong-Sik Kim was born in Seoul, Korea, on April 4, 1973. He received the B.S., M.S. and Ph.D. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea, in 1977, 1999, and 2004, respectively. He was a Post-Doctorial Fellow with the Institute of Virginia Technology. He is currently working on System LSI Group in the Samsung Electronics. His current research interest includes design-for-testability, built-in self tests and fault diagnosis. Sungho Kang received the B.S. degree from Seoul National University, Seoul, Korea, and the M.S. and Ph.D. degrees in electrical and computer engineering from The University of Texas at Austin. He was a Post-Doctorial Fellow with the University of Texas at Austin, a Research Scientist with the Schlumberger Laboratory for Computer Science, Schlumberger Inc., and a Senior Staff Engineer with the Semiconductor Systems Design Technology, Motorola Inc. Since 1994, he has been an Associate Professor with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea. His current research interests include VLSI design, VLSI CAD and VLSI testing and design for testability.     

一种简化的模拟电路测试性评价方法

模拟电路的测试性是进行故障诊断和定位的重要依据.采用基于符号化的分析方法来进行测试性评价,相对于数值计算的方法更有优势.提出了一种测试性矩阵的构建方法,同时给出并证明了基于该测试矩阵进行测试性评价的方法.该评价方法的特点是计算简单实用,且消除了计算误差.最后,通过电路实例,验证了该方法的有效性及其实现上的简洁性.     

A New Testability Calculation Method to Guide RTL Test Generation

Current paper presents a unified approach for calculating mixed-level testability measures. In addition, a new method of testability guided RTL Automated Test Pattern Generation (ATPG) for sequential circuits is introduced. The methods and algorithms are based on path tracing procedures on decision diagrams. The previous known methods have been implemented in test synthesis and in guiding gate-level test generation. However, works on application of testability measures to guide high-level test generation are missing. The main aim of this paper is to bridge this gap. Current method is compared to a recent approach known from the test synthesis area. Experiments show that testability measures greatly influence the fault coverage in RT-level test generation with the proposed approach achieving the best results. Similar to earlier works, our research confirms that RT-level fault coverage is in correlation with logic level one.This revised version was published online in March 2005 with corrections to the cover date.