Threshold reduction for demodulating a BPSK suppressed-carrier signal (Corresp.)

If a Costas loop is forced to have a relatively wide bandwidth, for example, to track phase variation due to platform motion, binary phase-shift keying (BPSK) demodulator performance is significantly degraded. However, if the data bits were known, the Costas loop would become equivalent to a phase-locked loop, which has approximately a 6-dB lower tracking threshold for the same loop bandwidth. A delayed-bit estimation algorithm with a recursive structure similar to the Viterbi algorithm is described. The memory in the tracking loop is exploited to correct preliminary bit decisions, as a means of realizing most of this theoretical threshold reduction. Experimental results for a practical digital implementation of the new algorithm for a 50-bit/s data rate and a 20-Hz loop noise bandwidth show a 4-dB improvement in demodulator threshold.     

Costas Loop Experiments for a 10.6 µm Communications Receiver

We have transferred the principle of the Costas-type nonlinear phase-locked loop to thelambda = 10.6 mum wavelength of CO2lasers. The ability of the optical Costas loop to regenerate the carrier of a binary phase-shift-keyed input signal and to perform coherent demodulation was demonstrated at a data rate of 20 Mbits/s.     

Performance analysis of optical heterodyne PSK receivers in thepresence of phase noise and adjacent channel interference

A phase-shift-keying (PSK) optical heterodyne receiver using synchronous detection by means of a Costas phase-locked loop (PLL) is investigated. Taking into account the laser phase noise and adjacent channel interference (ACI), an expression of the phase error variance is derived and error probability calculation is performed. Plots of the error probability versus the number of photons per bit are presented as a function of the optical domain channel spacing (D) and for several linewidth-to-bit-rate ratios (δf/R_b ). Relative sensitivity penalties, based on the performance with and without ACI, are evaluated for several combinations of D and δf/R_b. It is shown that, if lasers with larger linewidths are used, the frequency separation between optical carriers has to be increased in order to allow the same relative sensitivity penalty     

Properties of Optical Phase-Locked Loop Based on Four Wave Mixing in Semiconductor Laser Amplifiers

In this paper, the properties of the optical phase-locked loop(PLL) based on the four-wave mixing in the semiconductor laser amplifiers (SLAs) are discussed. The components that achieve the function of detecting the bit phase of the input optical signal are concerned and discussed in detail together as a function module named as the optical bit phase detector referred to the general electronic PLL. Therefore, most of the properties of the optical PLL can be analyzed by applying the general phase-locked theory. Here the stability of the optical PLL is discussed. It's shown that the variance of input signal power in the practical application will cause optical PLL system unstable because of its long loop delay. The influence on the output phase jitter of the optical PLL is also investigated.     

适用于无人机图像传输数据链的同步技术

所述技术用于无人机下行数据链图像传输系统,该系统的设计基于软件无线电的思想,属于突发通信。针对该系统采用了Pi/4-QPSK调制、全数字接收机,在接收机中采用Farrow内插滤波、Gardner定时误差算法来实现位同步和采用Costas锁相环来实现载波同步。针对这两种技术进行了研究与Matlab仿真分析。仿真结果证明了该方案的可行性和优越性,且易于硬件实现。     

基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

利用TSMC的O．18μm CMOS工艺,设计实现了单片集成的5 Gb/s锁相环型时钟恢复电路。该电路采用由半速率鉴相器、四相位环形电流控制振荡器、电荷泵以及环路滤波器组成的半速率锁相环结构。测试表明：在输入速率为5 Gb/s、长度为211-1伪随机序列的情况下,恢复出时钟的均方根抖动为4．7 ps。在偏离中心频率6MHz频率处的单边带相位噪声为-112．3 dBe/Hz。芯片面积仅为0．6mm×O．6 mm,采用1.8 V电源供电,功耗低于90 mW。     

1-Gsymbol/s 64-QAM Coherent Optical Transmission Over 150 km

Quadrature amplitude modulation (QAM) is an excellent modulation format for realizing optical communication systems with a high spectral efficiency of much greater than 1bit/s/Hz. We describe QAM coherent optical communication that we achieved by using heterodyne detection with a frequency-stabilized fiber laser and an optical phase-locked loop (OPLL) technique. The phase error variance of the intermediate frequency signal of the OPLL was 6.1times10^-3 rad. A 1-Gsymbol/s 64-QAM coherent signal was successfully transmitted over 150km     

注入同步锁相环式时钟恢复电路MMIC的设计和实现

设计了单片集成的超高速NRZ码时钟恢复电路,该电路采用注入同步压控振荡器结合锁相环的结构,在保持普通PLL型时钟恢复电路优点的同时,加快了锁相环的响应速度,提高了系统的稳定度。利用法国OMMIC公司的0.2μmGaAsPHEMT,制造了MMIC芯片,在输入速率为8.2Gb/s、长度为223-1伪随机序列的情况下,输出时钟的均方根抖动为1.6ps。芯片面积为1.5mm×2mm。采用-5V电源供电,功耗约为600mW。     

数字Costas锁相环的改进及应用

介绍了Costas锁相环的基本原理,然后提出了一种适合电视信号色度副载波恢复的改进数字Costas锁相环的基本原理.并且详细介绍了其积分清零器、相位检测器、数字环路滤波器、NCO等各个基本部件的设计,最后在Matlab上给出了该算法的仿真结果并且做了分析.     

4-Gb/s PSK homodyne transmission system using phase-lockedsemiconductor lasers

Homodyne detection of 4-Gb/s pilot-carrier binary-phase-shift-keyed (BPSK) optical signals using external-cavity semiconductor lasers synchronized by a linear phase-locked loop is discussed. A 2¹⁵-1 pseudorandom binary sequence (PRBS) has been transmitted through a short fiber with a receiver sensitivity of -44.2 dBm or 72 photons/bit. After transmission through 167 km of standard single-mode fiber, the sensitivity is -43.6 dBm or 83 photons/bit. A balanced PIN/HEMT transimpedance receiver which has a 3-dB bandwidth from 100 kHz to 10.1 GHz and an average equivalent input noise current of 10.8 pA/√Hz is used     

An optical PSK homodyne transmission experiment using 1320 nmdiode-pumped Nd:YAG lasers

A second-order optical phase-locked loop was constructed using 1320-nm diode-pumped miniature Nd:YAG ring lasers. Using the loop, a 140-Mb/s PSK homodyne transmission experiment was demonstrated over 28.6 km of single-mode fiber. With a loop natural frequency of 13 kHz and a damping factor of 0.6, the receiver sensitivity was -62.8 dBm, or 25 photons/bit. The authors believe this is the highest sensitivity obtained to date with any optical communication system     

Performance of optical heterodyne PSK systems with Costas loop inmultichannel environment for nonlinear second-order PLL model

Using the nonlinear second-order phase-locked loop (PLL) model the performance of the heterodyne coherent optical phase shift keying (PSK) systems with Costas loop in multichannel environment is considered in this paper for the first time. The shot noise of the corresponding photodiodes and adjacent channel interferences are described through the signal-to-noise ratio (SNR) in the loop bandwidth, while the laser phase noise is described through the normalized frequency fluctuations instead of the phase ones. The theory and results presented in this paper can be applied when analyzing and optimizing the performance in the region where the linear PLL model is not enough good     

The use of interleaving for reducing noisy reference loss intrellis-coded modulation systems

The use of interleaving/deinterleaving in trellis-coded modulation systems to reduce the SNR loss due to imperfect carrier demodulation references is demonstrated. Both the discrete carrier (phase-locked loop) and the suppressed carrier (Costas loop) cases are considered, and the differences between the two are clearly demonstrated by numerical results. The special case of convolutional codes is also treated and illustrated with an example of practical interest     

Carrier synchronization for homodyne and heterodyne detection ofoptical quadriphase-shift keying

Through analysis and simulation, the authors investigated the performance of four carrier-synchronization techniques suitable for both homodyne and heterodyne detection of optical quadriphase-shift keying: the discrete-time decision-directed loop, the analog decision-directed loop, the Costas quadriphase loop, and the fourth-power phase-locked loop. Accounting for shot noise, laser phase noise, and feedback delay, they optimize the loop natural frequency and specify laser-linewidth requirements. The performance discrepancy between the best and worst of these loops is found to be small; accounting for inherent loop delays only, the linewidth requirements range from ΔvT<2.5×10^-5 to ΔvT<5.2×10^-5, where Δv is the beat laser linewidth and T is the baud interval. Hence other considerations, such as ease of implementation, will govern the design choice for most practical systems. For the case when propagation delays in the feedback loop are significant, a simple and accurate method for estimating the laser-linewidth requirement and corresponding optimal natural frequency is presented     

A 622-Mb/s bit/frame synchronizer for high-speed backplane datacommunication

A compact 622-Mb/s/port bit/frame synchronizer is presented. Sampling equally-phased clocks from a phase-locked loop (PLL) at the data transition edges, the bit synchronizer selects the optimum one as the extracted clock. An elastic serial-to-parallel converter is used for the frame synchronization. The circuit is designed for a 32-port ATM switch chip, achieving 622-Mb/s port capacity by four parallel 156-Mb/s bits. Using 0.5-μm CMOS technology, the circuit was verified by simulations. The bit synchronizer consumes only 15 mW under typical conditions     

560 Mb/s optical PSK synchronous heterodyne experiment

A phase-locked optical heterodyne receiver constructed using a 1320-nm diode-pumped miniature Nd:YAG ring laser is discussed. Using this receiver and a transmitter based on another Nd:YAG laser, a 560-Mb/s phase-shift keying (PSK) synchronous heterodyne transmission was demonstrated over 78 km of single-mode fiber. With an optical phase-locked loop (PLL) natural frequency of 32 kHz and a damping factor of 1.46, the receiver sensitivity, measured at the output of the transmission link, was -48.7 dBm, or 159 photons/b. The corresponding detected sensitivity, measured on the surface of the p-i-n diode, was -51.8 dBm or 78 photons/b. This result suggests that the receiver sensitivity would have been about 82 photons/b if a balanced receiver with 0.2-dB excess coupler loss had been used. The impact of the finite intermediate frequency (IF) on heterodyne system performance was investigated; it was found that an IF of at least twice the bit rate is needed for a negligibly small penalty     

Slot clock recovery in optical PPM communication systems withavalanche photodiode photodetectors

Slot timing recovery in a direct-detection optical PPM communication system can be achieved by processing the photodetector output waveform with a nonlinear device whose output forms the input to a phase-locked loop. The choice of a simple transition detector as the nonlinearity is shown to give satisfactory synchronization performance. The RMS phase error of the recovered slot clock and the effect of slot timing jitter on the bit error probability were directly measured. The experimental system consisted of an AlGaAs laser diode (λ=834 nm) and a silicon avalanche photodiode photodetector. The system used Q =4 PPM signaling and operated at a source data rate of 25 Mb/s. The mathematical model developed to compute the RMS phase error of the recovered clock is shown to be in good agreement with results of actual measurements of phase errors. The use of the recovered slot clock in the receiver resulted in no significant degradation in receiver sensitivity compared to a system with perfect slot timing. The system achieved a bit error probability of 10^-6 at a received optical signal energy of 55 detected photons per information bit     

On false lock in suppressed carrier MPSK tracking loops

The problem of false lock in suppressed-carrier minimum phase-shift keying (MPSK) tracking loops (M>4 in particular), such as Mth power phase-locked loop (PLL) and MPSK Costas loop carrier recovery subsystems, is investigated. It is demonstrated that such tracking loops false lock onto the received signal when the received carrier frequency and the reference signal frequency generated by MPSK tracking loops are mismatched by multiples of 1/M of the MPSK symbol rate. False lock margins (FLMs) for the suppressed carrier MPSK tracking loops are obtained for a noiseless system model as well as for a model corrupted by additive white Gaussian noise (AWGN). Numerical results are presented in order to explain the influence of system parameters, such as the time-bandwidth product of MPSK Costas loop arm filters (or the Mth power PLL prefilter), arm filters' output signal-to-noise ratio and the input signal-to-noise ratio, on the performance of MPSK tracking loops     

W-band Communication System with Direct Frequency Shift Keying Modulation to Phase-locked Oscillator

Based on the theory of phase-locked loop, the analysis and simulation of direct frequency shift keying to phase-locked oscillator is presented. Then, a W-band digital communication system is developed, in which the millimeter wave phase-locked oscillator of the transmitter is modulated directly by 15grades 2048 kbit/s signal. The results of the experiment in the field show that the phase-locked loop has little influence on the modulating signal. It is a good way to simplify the transmitter configuration and suitable for high bit rate communication.     

The performance of optical phase-locked loops in the presence of nonnegligible loop propagation delay

The optical phase-locked loop is analyzed taking into account shot noise, phase noise, and loop propagation delay. The degradation of loop phase error due to propagation delay is evaluated in terms of the delay bandwidth productomega_{n} cdot tau_{D}. This product was found to have a maximum value of 0.736 for absolute loop stability. The resulting effect on a Costas loop system optimized for zero time delay is discussed. It is found that in order to maintain a 10^-9BER system performance withxi = 1/2^{0.5}, R = 0.85A/W,P_{DATA} = -59.2dBm, and a 1-MHz beat linewidth, the delay time must be kept below 1.8 ns. If the beat linewidth increases to 15 MHz this figure drops to 0.12 ns.