Complex bandpass sampling and direct downconversion of multiband analytic signals

The kernel concept of the software defined radio architecture is to eliminate the analogue mixers and to place analogue-to-digital converters as near the antenna as possible. Bandpass sampling can be used for direct downconversion without analogue mixers. In this paper, we report an efficient method to find the ranges of valid bandpass sampling frequency for direct downconverting multiple bandpass analytic signals (single-sideband RF signals). The algorithm results in the ranges of valid bandpass sampling frequency for the complex signals in terms of bandwidths and band positions of the single-sideband RF signals. Compared to real bandpass sampling, the valid sampling frequency ranges are easier to find and the ranges thus obtained having much wider interval than those of real sampling. As a consequence, the complex sampling scheme is more flexible in choosing sampling frequency and more robust to the sampling frequency variation. Furthermore, if spectral inversion is not permitted, then in some cases there will have no applicable sampling frequency under Nyquist rate for real sampling.     

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

Digital interpolation beamforming for low-pass and bandpass signals

Digital time-domain beamforming requires that samples of the sensor signals be available at a sufficient rate to realize accurate time delays for beam steering. For many applications, this input rate, which may be significantly higher than the Nyquist rate required for waveform reconstruction, places stringent requirements on A/D converter hardware and transmission cable bandwidth. Recently, a technique referred to as digital interpolation beamfonning was introduced which greatly relaxes the sampling requirement and provides substantial hardware savings through more flexible design options. In this approach, the sensor channels need only be sampled at a rate which satisfies aliasing requirements. The vernier beam-delay increments are then synthesized using digital interpolation which can be implemented at the beamformer input or output to minimize digital processing complexity. Previously, this concept was presented for the case of "low-pass" signals. This paper extends this work by examining the relationship between interpolation and beamforming for the important class of "bandpass" signals. Specifically, sampling methods are discussed whereby the original waveform can be reconstructed from samples taken at a rate consistent with the bandwidth of the bandpass signal. Beamformer implementations are presented which utilize these bandwidth-sampling techniques in conjunction with interpolation and which compute beam output points at the generally low rate dictated by the signal bandwidth. The interpolation beamformer achieves time-delay quantization (beam-steering accuracy) independent of both the input and output sampling rates. This approach generally requires less hardware than conventional procedures. Interpolation falter characteristics dictated by the bandwidth-sampling procedure are described and efficient methods of implementation employing nonrecursive digital bandpass and low-pass filters are presented.     

多带通信号直接均匀欠采样技术

该文讨论了宽带数字接收机中对多个复或实的带通信号的直接均匀采样。对这多个通带位置及带宽均是任意的实或复的带通信号给出了采样率应满足的关系,用此采样率采样使输入数据得到有效的压缩,同时结合滤波器将频谱进行搬移,最后给出了实例。     

一种新的数字阵列雷达接收机技术

高速ADC和先进DSP器件的进展使数字波束形成智能天线的实现成为现实。在传统的M单元天线阵系统中,每一单元都有各自的接收通道和ADC,设备量大。文中提出了一种适合于多通道数字阵列雷达接收系统的新型数字接收机结构,其主要思想是基于多个不同信号的带通采样原理实现数字阵列雷达接收机,新接收机结构使IF接收通道和基带采样ADC显著减少,功耗大大降低。阐述了数字阵列接收的数据模型和工作原理,分析了多信号带通采样信号频率和采样率的关系,给出了采样率选取的约束条件。新接收机在降低设备量的同时,还减小了接收系统通道间幅一相不一致性失真。     

Direct downconversion of multiband RF signals using bandpass sampling

Abstract-Bandpass sampling can be used by radio receivers to directly digitize the radio frequency (RF) signals. Although the bandpass sampling theory for single-band RF signals is well established, its counterpart for multiband RF signals is relatively immature. In this paper, we propose a novel and efficient method to find the ranges of valid bandpass sampling frequency for direct downconverting multiband RF signals. Simple formulas for the ranges of valid bandpass sampling frequency in terms of the frequency locations of the multiple RF bands are derived. The result can be used to design a multiband receiver for software defined radios.     

A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-/spl mu/m CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP/sub 3/ of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm/sup 2/.     

A generalization of nonuniform bandpass sampling

Nth-order nonuniform sampling is described for generalized bandpass signal frequency position, bandwidth, sampling rate, frequency-shift and phase-shift. A bandpass extension to the Nyquist criterion is derived, showing that restrictions on bandpass frequency position for odd orders of nonuniform sampling tend to zero as N tends to infinity. Bandpass interpolants based on the sinc function are derived for the generalized Nth-order sampled bandpass signals. It is shown that, for minimum (Nyquist) rate sampling, these interpolants are comprised of N bandpass filters, each with independent phase. The number of bandpass filters comprising the interpolant is found to decrease as the sample rate increases. The advantage of describing Nth-order sampling as the Nth replication and uniform sampling of a signal is demonstrated. Finally, digital implementation of the Nth-order bandpass sampling interpolants is discussed. It is established that it is not practicable to attempt to perform nonuniform bandpass sampling at the theoretical minimum rate, where the interpolation is to be performed digitally     

中频信号接收与处理电路研究

介绍了一种中频信号接收与处理电路设计,在研究了中频信号带通采样理论的基础上,设计了一种基于ADC+FPGA+DSP结构框架的中频信号接收与处理电路,对ADC转换器电路、FPGA及外围电路、DSP及其外围电路以及电源模块电路的设计进行了详细介绍。该中频信号接收与处理电路可以实现125MSPS的采样速率,FPGA和DSP的采用为后续信号处理提供了强大的硬件支持。因此,该中频信号接收与处理电路具有较高的实用价值。     

Combined linear and homomorphic deconvolutions for processingbandpass measurements [US flaw detection]

The deconvolution presented is a combination of available techniques. It is effective for extracting the impulse response of individual flaws from ultrasonic data generated by flaw clusters. The technique requires output signals from both the flawed and unflawed systems. By combining linear deconvolution and homomorphic deconvolution, using the complex cepstrum, the desired impulse response can be extracted in cases where the signals contain overlapping wavelets. For the important case of bandpass signals, for which the complex cepstrum does not exist, the technique can still be applied by including a bandpass mapping in conjunction with homomorphic processing. Application of this combined approach to ultrasonic signals reflected from epoxy specimens produced the impulse response of a single cavity from measurements which were bandpass and contained overlapping signals from adjacent cavities. The recovered response, which compared well with the theoretical response of a single cavity, was sufficiently resolved to yield the radius of the spherical cavity     

5.2/5.7-GHz 48-dB Image Rejection GaInP/GaAs HBT Weaver Down-Converter Using LO Frequency Quadrupler

A GaInP/GaAs heterojunction bipolar transistor (HBT) down-converter using the Weaver architecture is demonstrated in this paper. The Weaver system is a double-conversion image rejection heterodyne system which requires no bandpass filters in the signal path and no quadrature networks. The Weaver down-converter has the image rejection ratios of 48 dB and 44 dB when the RF frequency is 5.2 GHz and 5.7 GHz, respectively. A new frequency quadrupler is employed in the down-converter to generate the local oscillator (LO) signals. The frequency quadrupler is designed to minimize the phase error when generating LO signals and thus the image rejection performance is improved. A diagrammatic explanation using the complex mixing technique to analyze the image rejection mechanism of the Weaver architecture is developed in this paper. From our analysis, the image rejection can be further improved by making the LO₁ and LO₂ signals coherent     

Estimation of Aliasing Effects Due to Periodical Nonuniform Individual Sampling in High-Q Switched-Capacitor Filters

The periodical nonuniform individual sampling scheme has been shown suitable for capacitance spread and total capacitor area reduction in high quality (Q) factor switched-capacitor (SC) filters. However, the use of periodical nonuniform clock signals results in additional aliasing components in the output spectrum. This paper presents a simple model to analyze the generation of such alias components and gives practical expressions to estimate their power. The results are verified through circuit simulation of a 10.7-MHz second-order SC bandpass filter in a 0.35-mum CMOS technology. Implications on the use of this technique in the design of intermediate-frequency filters are discussed     

Direct bandpass sampling of multiple distinct RF signals

A goal in the software radio design philosophy is to place the analog-to-digital converter as near the antenna as possible. This objective has been demonstrated for the case of a single input signal. Bandpass sampling has been applied to downconvert, or intentionally alias, the information bandwidth of a radio frequency (RF) signal to a desired intermediate frequency. The design of the software radio becomes more interesting when two or more distinct signals are received. The traditional approach for multiple signals would be to bandpass sample a continuous span of spectrum containing all the desired signals. The disadvantage with this approach is that the sampling rate and associated discrete processing rate are based on the span of spectrum as opposed to the information bandwidths of the signals of interest. Proposed here is a technique to determine the absolute minimum sampling frequency for direct digitization of multiple, nonadjacent, frequency bands. The entire process is based on the calculation of a single parameter-the sampling frequency. The result is a simple, yet elegant, front-end design for the reception and bandpass sampling of multiple RF signals. Experimental results using RF transmissions from the US Global Positioning System-Standard Position Service (GPS-SPS) and the Russian Global Navigation Satellite System (GLONASS) are used to illustrate and verify the theory     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.     

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

This paper presents a clock generator circuit for a high-speed analog-to-digital converter (ADC). A time-interleaved ADC requires accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at a speed of 166 MS/s, which corresponds to an equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 μm SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies a 0.6 mm² silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted using 1 ps precision.     

A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators

In this paper, a bandpass analog-to-digital converter (ADC) based on time-interleaved oversampled ADC is introduced. Unlike previous delta–sigma bandpass ADCs that require accurate digital-to-analog converters and high-speed analog circuits, the proposed architecture provides bandpass function by time-interleaving first-order voltage-controlled-oscillator (VCO)-based ADCs. The use of VCO-based ADC has the advantage that its resolution is determined by the time resolution rather than the voltage resolution, thus making it attractive for future low-voltage CMOS processes. The performance of the proposed ADC is theoretically analyzed and simulated in ideal condition, as well as in nonideal condition, in the presence of nonlinearity, sampling clock jitter, and mismatch.      

Extended frequency-band-decomposition sigma–delta A/D converter

Parallelism can be used to increase the bandwidths of ADC converters based on sigma–delta modulators. Each modulator converts a part of the input signal band and is followed by a digital filter. Unfortunately, solutions using bandpass sigma–delta modulators are very sensitive to the position of the modulators’ central frequencies. This paper shows the feasibility of a frequency-band-decomposition (FBD) ADC using continuous time bandpass sigma–delta modulators, even in the case of large analog mismatches. The major benefit of such a solution, called extended-frequency-band-decomposition (EFBD) is its low sensitivity to analog parameters. For example, a relative error in the central frequencies of 4% can be accepted without significant degradation in the performance (other published FBD ADCs require a precision of the central frequencies better than 0.1%). This paper will focus on the performance which can be reached with this system, and the architecture of the digital part. The quantization of coefficients and operators will be addressed. It will be shown that a 14 bit resolution can be theoretically reached using 10 sixth-order bandpass modulators at a sampling frequency of 800 MHz which results in a bandwidth of 80 MHz centered around 200 MHz (the resolution depends on the effective quality factor of the filters of the analog modulators).     

A Method to Reduce Sampling Rate of the ADC in Feedback Channel for Wideband Digital Predistortion

This paper presents a new digital predistortion (DPD) solution for wideband signals with low feedback sampling rate. To reduce the minimum sampling rate of the analog-to-digital converter (ADC) for wideband digital predistortion, the proposed method uses a bandpass filter to form a narrowband signal before the ADC. Then, a deconvolution operation is performed to recover the original wideband signal from the ADC samples. The proposed method is evaluated with an international mobile telecommunication-advanced signal with 100 MHz bandwidth. The simulation results show that the recovered signal of the proposed method closely approximates to the original signal in the passband of the filter, and the mean square error of the deconvolution decreases as the signal-to-noise ratio increases. The proposed algorithm can reduce the sampling rate of the ADC from 1105.92 million samples per second (MSPS) to 368.64 MSPS, and improve the adjacent channel power ratio more than 20 dB, which is merely 5.6 dB less than the conventional DPD with 1105.92 MSPS sampling rate.     

欠采样带通信号时延估计算法

本文研究了带通信号的时延估计问题。由于带通信号载波的高频振荡,已有的时延估计算法在欠采样条件下无法得到精确的估计结果,尤其当延时真值不是采样间隔整数倍时,将出现无法克服的误差平台。本文通过分析,对这一问题给出了合理的解释,并提出了一种欠采样条件下的带通信号时延估计新算法。新算法利用相关函数的复包络估计时延很好地解决了上述问题,进而利用带通信号的特点提高了算法对噪声的鲁棒性。仿真结果说明,新算法的性能优于已有的时延估计算法。     

Joint angular and spectral estimation technique using nonlinear Kalman filters for cognitive radio

The joint estimation of direction of arrivals (DOA) and carrier frequencies of band-limited source signals is considered in this paper. A novel technique based on nonlinear Kalman filters is proposed for this joint angular and spectral estimation problem for cognitive radio (CR). Since sampling a wideband spectrum at Nyquist rate increases the analog-to-digital converter (ADC) requirements, we propose executing Kalman filter algorithm over a spatial state space model. Thus, one time sample is required and hardware complexity is reduced. Two types of nonlinear Kalman filters, extended Kalman filter (EKF) and unscented Kalman filter (UKF), are proposed. We consider their sub-optimal performance and show how to control their convergence. However, the proposed algorithms can detect a number of source signals limited to the number of elements in employing arrays.