Highly linear 0.18-/spl mu/m CMOS power amplifier with deep n-Well structure

The linearity of a 0.18-/spl mu/m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C/sub gs/), which is the dominant nonlinear source, and partially from drain junction capacitance (C/sub jd/). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-/spl mu/m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P/sub out/, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P/sub 1dB/. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P/sub out/, 18.9 dB of power gain and 35% of PAE at P/sub 1dB/. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.     

A 4-W X-band compact coplanar high-power amplifier MMIC with 18-dB gain and 25% PAE

The performance of a compact coplanar microwave monolithic integrated circuit (MMIC) amplifier with high output power in the X-band is presented. Based on our 0.3-/spl mu/m gate-length GaAs power pseudomorphic high electron mobility transistor (PHEMT) process on 4-in wafer, this two-stage amplifier, having a chip size of 16 mm/sup 2/, averages 4-W continuous-wave (CW) and 25% mean power-added efficiency (PAE) in the X-band, with more than 18-dB linear gain. Peak output powers of P/sub -1dB/=36.3dBm (4.3 W) and P/sub sat/ of 36.9 dBm (4.9 W) at 10 GHz with a PAE of 50% were also measured. Compared to previously reported X-band coplanar high-power amplifiers, this represents a chip size reduction of 20%, comparable to the size of compact state-of-the-art microstrip power amplifiers.     

A Handset Power Amplifier With High Efficiency at a Low Level Using Load-Modulation Technique

A new monolithic-microwave integrated-circuit power amplifier for cellular handsets has been implemented using the load-modulation concept of the Doherty amplifier, which has a high efficiency at a low power level. In order to get a compact module, the$lambda/4$transmission line for the load modulation is replaced by a passive high-pass$pi$-network, and the load-modulation circuit is also modified to function as a power-matching circuit of the main amplifier. The amplifier has two modes of operation, low- and high-power modes, controlled by a control voltage. At the high power mode, both the main and auxiliary amplifiers are operational and, at the low power mode, only the main amplifier generates output power enhancing the efficiency. For the code-division multiple-access environment, the amplifier at the low-power mode provides power-added efficiency (PAE) of 39.8% and an adjacent channel power ratio (ACPR) less than 49.8 dBc at 23.1 dBm, and the high-power mode PAE of 37.9% and ACPR of 46.4 dBc at 28 dBm. The efficiency is improved by approximately 18.8% at$ P_ out=23$dBm by the load-modulation technique. For the advanced mobile phone system-mode operation, the amplifier delivers 26.1 dBm with PAE of 53% and 30.8 dBm with 48.7% at the low and high modes, respectively.     

Two-stage quasi-class-E power amplifier in GaN HEMT technology

This letter presents a two-stage quasi-class-E monolithic microwave integrated circuit power amplifier at 2.0GHz, which is based on field-plated GaN high electron mobility transistor technology. It consists of a driver stage and a power stage. The circuit schematic is described. The amplifier achieves an output power of 37.5dBm into a 50-/spl Omega/ load, a power added efficiency (PAE) of 50%, and a gain of 18.2dB. A power density of 5.6W/mm is achieved.     

A highly linear and efficient differential CMOS power amplifier with harmonic control

A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-/spl mu/m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g/sub m3/ and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5dBm of P/sub 1dB/ with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under -45 dBc of IMD3 and -57dBc of IMD5 when the output power is backed off by more than 5dB from P/sub 1dB/. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification.     

An InGaP-GaAs HBT MMIC smart power amplifier for W-CDMA mobile handsets

We demonstrate a new linearized monolithic microwave integrated circuit smart power amplifier of extraordinary high power-added efficiency (PAE), especially at the most probable transmission power of wide-band code-division multiple-access handsets. A PAE of 21% at 16 dBm of output power, which is the maximum bound of the most probable transmission power in IS-95 systems, was obtained, as well as 40% at 28 dBm, the required maximum output power, with a single-chip MMIC power amplifier. The power amplifier has been devised with two InGaP-GaAs heterojunction bipolar transistor amplifying chains parallel connected, each chain being optimized for a different P/sub 1dB/ (1-dB compression point) value: one for 16 dBm for the low-power mode, targeting the most probable transmission power, and the other for 28 dBm for the high-power mode. The high-power mode operation shows 40% of PAE and -30 dBc of adjacent channel leakage power ratio (ACLR) at the maximum output power of 28 dBm. The low-power mode operation exhibits -34 dBc of ACLR at 16 dBm with 14 mA of a quiescent current. This amplifier improves power usage efficiency and, consequently, the battery lifetime of the handset by a factor of three.     

A 21-26-GHz SiGe bipolar power amplifier MMIC

A three-stage 21-26-GHz medium-power amplifier fabricated in f/sub T/=120 GHz 0.2 /spl mu/m SiGe HBT technology has 19 dB small-signal gain and 15 dB gain at maximum output power. It delivers 23 dBm, 19.75% PAE at 22 GHz, and 21 dBm, 13% PAE at 24 GHz. The differential common-base topology extends the supply to BV/sub CEO/ of the transistors (1.8 V). New on-chip components, such as onchip interconnects with floating differential shields, and self-shielding four-way power combining/dividing baluns provide inter-stage coupling and single-ended I/O interfaces at the input and output. The 2.45/spl times/2.45 mm/sup 2/ MMIC was mounted as a flipchip and tested without a heatsink.     

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.     

基于SiGe工艺的高增益射频功率放大器

基于0.13μm SiGe HBT工艺,设计应用于无线局域网(WLAN)802.11b/g频段范围内的高增益射频功率放大器.该功放工作在AB类,由三级放大电路级联构成,并带有温度补偿和线性化的偏置电路.仿真结果显示:功率增益高达30dB,1dB压缩点输出功率为24dBm,电路的S参数S11在1.5～4GHz大的频率范围内均小于-17dB,S21大于30dB,输出匹配S22小于-10dB,S12小于-90dB.最高效率可达42.7%,1dB压缩点效率为37%.     

CMOS RF power amplifier with reconfigurable transformer

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.     

Effects of output harmonic termination on PAE and output power of AlGaN/GaN HEMT power amplifier

The authors experimentally investigate and discuss the effects of output harmonic termination on power added efficiency (PAE) and output power of an AlGaN/GaN high electron mobility transistor (HEMT) power amplifier (PA). The AlGaN/GaN HEMT PA with gate periphery of 1 mm was built and tested at L-band. Large-signal measurements and comparisons of the PAE and output power were carried out at different DC bias conditions from 50% of saturated drain current (I/sub dss/) to 1% of Id., for the PA with and without output harmonic termination. For class-AB operation at 25% of I/sub dss/, an increase of about 10% in peak PAE and 1 dBm in output power were observed in saturated output power range. Improvements of up to 9% in PAE and 1.2 dBm in output power were achieved over the measured DC bias conditions provided the output harmonics are properly terminated.     

A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier

A two-stage self-biased cascode power amplifier in 0.18-/spl mu/m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.     

A +31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications

A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky lambda/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8times3.2mm² including all pads and bypass capacitors     

High Efficiency RF Power Amplifier Designed With Harmonic Real-Time Active Load-Pull

In this work, a high efficiency p-HEMT radio frequency power amplifier (PA) is designed using a new multiharmonic real-time active load-pull using the large signal network analyzer. This technique synthesizes a large set of instantaneous load mismatches to quickly find the optimal harmonic impedances, so as to achieve high PA efficiency in a shortened design cycle. At 2 GHz a demo power amplifier implemented with a p-HEMT demonstrated a power added efficiency (PAE) of 68.5% for 18.0 dBm output power, while achieving a maximum PAE of 75% below the 1 dB compression point for 18.6 dBm output power.     

A 5.7-GHz 0.18-/spl mu/m CMOS gain-controlled differential LNA with current reuse for WLAN receiver

This letter presents a 5.7 GHz 0.18 /spl mu/m CMOS gain-controlled differential LNA for an IEEE 802.11a WLAN application. The differential LNA, fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process, uses a current-reuse technology to increase linear gain and save power consumption. The circuit measurement is performed using an FR-4 PCB test fixture. The LNA exhibits a noise figure of 3.7 dB, linear gain of 12.5 dB, P/sub 1dB/ of -11 dBm, and gain tuning range of 6.9 dB. The power consumption is 14.4 mW at V/sub DD/=1.8 V.     

A fully integrated 5.3-GHz 2.4-V 0.3-W SiGe bipolar power amplifier with 50-/spl Omega/ output

A radio frequency power amplifier for 4.8-5.7 GHz has been realized in a 0.35-/spl mu/m SiGe bipolar technology. The balanced two-stage push-pull power amplifier uses two on-chip transformers as input-balun and for interstage matching. Further, it uses three coils for the integrated LC-output balun and the RF choke. Thus, the power amplifier does not require any external components. At 1.0-V, 1.5-V, and 2.4-V supply voltages, output powers of 17.7 dBm, 21.6 dBm, and 25 dBm are achieved at 5.3 GHz. The respective power-added efficiencies (PAE) are 15%, 22%, and 24%. The small-signal gain is 26 dB. The output 1-dB compression point at 2.4 V is 22 dBm with a PAE of 14%.     

A 500-600 MHz GaN power amplifier with RC-LC stability network

A 500-600 MHz high-efficiency, high-power GaN power amplifier is designed and realized on the basis of the push-pull structure. The RC-LC stability network is proposed and applied to the power amplifier circuit for the first time. The RC-LC stability network can significantly reduce the high gain out the band, which eliminates the instability of the power amplifier circuit. The developed power amplifier exhibits 58.5 dBm (700 W) output power with a 17 dB gain and 85% PAE at 500-600 MHz, 300 μs, 20% duty cycle. It has the highest PAE in P-band among the products at home and abroad.     

Dual-Gate MESFET Variable-Gain Constant-Output Power Amplifier

The use of a dual-gate GaAs FET as a broad-band variable gain and constant output power amplifier is described. A five-stage variable gain-constant output power amplifier has been realized which provides a constant output power of 3 dBm (/spl plusmn/2 dB) for a large dynamic range of input power of -45 dBm to 0 dBm over the 4-8-GHz band. The amplifier uses a feed-forward AGC circuit for preadjusting the gain of the amplifier stages depending upon the strength of the signal at the output of preceding stages. The amplifier has the capability of detecting two or more simultaneous RF pulses having different amplitudes and separated by more than 15-ns time intervals. Also it preserves any amplitude modulation of the individual pulse.     

基于InGaP/GaAs HBT的X波段MMIC功率放大器研制

研制了X波段的InGaP/GaAs HBT单级MMIC功率放大器,该电路采用自行开发的GaAs HBT自对准工艺技术制作.电路偏置于AB类,小信号S参数测试在8～8.5GHz范围内,线性增益为8～9dB,输入驻波比小于2,输出驻波比小于3,优化集电极偏置后,线性增益为9～10dB.在8.5GHz进行连续波功率测试,在优化的负载阻抗条件下,P1dB输出功率为29.4dBm,相应增益7.2dB,相应PAE〉40%,电路的饱和输出功率Psat为30dBm.     

Equivalent Circuit of the Bolometer Detector

A small-signal dynamic equivalent circuit is established for the output voltage of a dc-biased bolometer (barretter) detector. The circuit consists of a voltage generator /spl upsi//sub g/, whose output is an undistorted replica of the incident RF-power modulation envelope, followed by a series resistor R/sub 1/ of dynamic origin, a shunt capacitor C that represents heat storage in the bolometer wire, and a series resistor R/sub 0/ equal to the dc resistance, usually 200 ohms. The resistance R/sub 1/ is independent of signal level, and is typically about 220 ohms for an 8.75-mA bolometer and about 120 ohms for a 4.5-mA bolometer. At a modulation frequency f/sub m/ near 0 Hz, the equivalent audio source impedance of the bolometer is R/sub 1/ +R/sub 0/. The common belief that the source impedance is R/sub 0/ in the weak-signal case is, therefore, refuted. Formulas are derived giving v/sub g/ / /P/sub RF/ and R/sub 1/ as functions of basic, easily determined bolometer parameters. The time constant for open-circuit load is /spl tau//sub oc/= R/sub 1/C, where /spl tau//sub oc/ is determined best by measurement, since catalog values of /spl tau//sub oc/ often are seriously in error. The capacitance is C=/spl tau//sub oc/ / /R/sub 1/. With one type of bolometer /spl tau//sub oc/ measures about 110 /spl mu/s, while various catalogs state values of 250 to 350 /spl mu/s. The equivalent circuit is confirmed quantitatively by measurements of output voltage and source impedance versus modulation frequency.