An analysis of deep depletion thin-film MOS transistors

Consideration is given to the problems associated with the use of an insulated gate to obtain depletion in the channel of a field-effect transistor. It is shown that if an inversion layer forms at the insulator semiconductor interface before the channel is completely depleted complete pinch-off of drain current by the gate will not be observed. It is further shown that channel pinch-off at the drain will always occur and, hence, that drain current saturation will always be observed. A quantitative analysis based on the proposed model is performed and theoretical expressions for the device behavior are derived and plotted. The analysis of the device is divided into two ranges, a high-frequency range and a low-frequency range, where the dividing frequency is the frequency response of the surface inversion layer. This dividing frequency is generally orders of magnitude lower than the upper operating frequency limit of the transistor itself. Finally, the theoretical results are compared with experiment and shown to be in good agreement.     

Scaled silicon MOSFETs: degradation of the total gate capacitance

We use a fully quantum-mechanical model to study the influence of image and exchange-correlation effects on the inversion layer and total gate capacitance in scaled Si MOSFETs. We show that, when the device is in weak and moderate inversion, the inclusion of image and many-body exchange-correlation effects increases both the inversion layer and total gate capacitances and shifts the N_s=N_s(VG) characteristics of the device toward lower gate voltages     

A simple model for quantum mechanical effects in hole inversionlayers in silicon PMOS devices

The effects of quantization of the inversion layer of MOSFET devices is an area of increasing importance as technology is aggressively scaled below 0.25 μm. Although electron inversion layers have attracted considerable interest, very little work has been reported for holes. This paper describes the implementation and results of a simple, computationally efficient model, appropriate for device simulators, for predicting the effects of hole inversion layer quantization. This model compares very favorably with experimental results and the predictions of a full-band, self-consistent Schrodinger-Poisson solver     

Experimental demonstration of an ultra-fast double gate inversion layer emitter transistor (DG-ILET)

In this letter we demonstrate experimentally a novel ultra-fast power device structure termed the double gate inversion layer emitter transistor (DG-ILET). The device is made in HV CMOS technology and its operation is based on a new physical injection mechanism previously reported and demonstrated experimentally (Udrea et al., 1996), namely the use of a MOS inversion layer as a minority carrier injector. The DG-ILET offers very fast turn-off associated with anode shorted lateral IGBT structures and low on-state voltage drop similar to standard lateral IGBTs without anode shorts. Unlike anode shorted structures, the DG-ILET does not exhibit a long, undesirable on-state snapback.     

Analysis and design of the dual-gate inversion layer emitter transistor

The dual-gate inversion layer emitter transistor (DGILET) is a device in which the injection of minority carriers takes place from an inversion layer formed under a MOS gate. Therefore, the device can be switched between MOS and bipolar modes using the gate giving the means to achieve a superior combination of low conduction losses and low switching losses. The structure of the device and operation in both the unipolar and bipolar modes are described in detail. Devices have been fabricated on bulk silicon wafers using junction isolation and experimental results confirm the expected superior performance. In particular, the results confirm predictions that if the inversion layer injector is properly designed, the voltage snapback that occurs during the transition between unipolar and bipolar modes can be completely suppressed. This can be achieved with a compact structure in contrast to the extended structures required in anode-shorted lateral insulated gate bipolar transistor (LIGBTs). An equivalent circuit for the DGILET is presented and the control of the minority carrier injection is also analyzed. Experimental results show that the DGILET can switch at speeds approaching those characteristic of MOSFETs with operating current densities comparable to LIGBTs. The results show that the DGILET offers lower overall losses than an LIGBT at switching frequencies above about 10 kHz.     

Detailed investigation of n-channel enhancement 6H-SiC MOSFETs

Basic MOSFET parameters like inversion layer mobility, threshold voltage, intrinsic mobility reduction factor and interface state density extracted from the subthreshold slope were examined in detail for 6H-SiC enhancement-mode n-channel MOSFETs. The inversion layer mobility and the threshold voltage were determined as a function of substrate doping concentration as well as device temperature. The interface state density was studied for different substrate doping concentrations. The inversion layer mobility was found to decrease strongly with increasing substrate doping. In contrast to earlier reports the inversion layer mobility decreases also with temperature. Furthermore, the threshold voltage depends more pronounced on substrate doping and temperature than theoretically expected. The interface state density extracted from the subthreshold slope increases significantly with substrate doping concentration. All these phenomena are consistently interpreted by the classical MOSFET behavior which is extended by acceptor like interface states. These states are located close to the conduction band and exhibit a density increasing drastically toward the band edge     

Theoretical studies of electronic conduction and optical generationmechanisms in the double-heterostructure optoelectronic switch (DOES)

The effects of other physical properties on the electrical and optical properties of the double-heterostructure optoelectronic switch device are calculated. The device is similar to an earlier version, but the charge sheet responsible for the unique electrical and optical switching properties of the device is placed in the wide-bandgap barrier layer rather than in the narrow-bandgap active layer. This generally improves the overall operating characteristics of the device because in principle it allows higher charge sheet doping values. This is possible because the charge sheet remains ionized even for very high inversion channel densities     

Simulation and comparison of MOS inversion layer quantum mechanics effects in SiGe PMOSFET and Si PMOSFET

By employing the semiconductor device 2D simulator Medici, the inversion layer quantum mechanics effects (QME) in the strained SiGe-channel PMOSFET are studied. The influences of the inversion layer QME on the channel hole sheet density, the surface potential, the electric field and the threshold voltage in strained SiGe PMOS and Si PMOS are simulated and compared. It is theoretically predicted and validated by the numeric simulation results that QME lead to much difference in device performance between SiGe PMOS and Si PMOS. This study shows that SiGe PMOS suffers less disadvantageous influence when compared with Si PMOS, in ultra-deep submicron dimension, where QME are becoming increasingly more important.     

Thermal resistance of MIS mesa varactors

The thermal resistance of MIS mesa varactors is calculated and measured. Results are given for varactors in a diode package as a function of device diameter. The measurement technique used is based on the temperature dependence of the inversion layer generation time.     

A mobility model for carriers in the MOS inversion layer

A mobility model for carriers in the MOS inversion layer is proposed. The model assumes that mobility is a function of the gate and drain fields, and the doping density, which conforms to Thornber's scaling law. Two-dimensional computer simulation combined with the present mobility model can predict experimental drain current within an error of ± 5 percent. The present model is applicable and suitable for designing short-channel MOSFET's, especially in the submicrometer range. The "saturation velocity" in the MOS inversion layer is also discussed, based on Thornber's scaling law. The saturation velocity, as determined from the calculated drain current in the same way as experimentalists have done, is 6.6 × 10⁶cm/s. This is close to what has been claimed to be "saturation velocity in the inversion layer," and is about two-thirds of microscopic saturation velocity. This lower saturation velocity originates from the nonuniform field distribution in the test device, and, therefore, the experimentally reported saturation velocity in the MOS inversion layer is inferred to be a macroscopic average, rather than the microscopic drift velocity.     

A study on the physical mechanism in the recovery of gatecapacitance to Cox in implanted polysilicon MOSstructures

The anomalous CV characteristics of MOS capacitor structures with implanted n⁺ polysilicon gate and p-type silicon substrate are studied through physical device simulation and experimental characterization over a wide range of frequencies and temperatures ranging from 100 to 250 K. It is shown that this anomalous CV behavior can be fully explained by the depletion of electrons and the formation of a hole inversion layer in the polysilicon gate due to energy band bending. The use of transistor structures for characterizing the polysilicon gate electrode is proposed. The results suggest thermal generation rather than impact ionization to be the dominant physical mechanism in supplying holes required by the inversion layer at the polysilicon-SiO₂ interface. This result also implies that hot-hole injection from the polysilicon gate into the SiO ₂ gate dielectric should not present a serious problem in device reliability     

非量子限条件下P型InSbMOS结构反型层中子能带实验研究

在100K条件下测量了p型InSb MOS器件的变频电容-电压(C-V)谱,在反型区观察到第二子带填充电子的台阶效应,还发现一个位于导带中的共振缺陷态.采用非量子限多带C-V拟合模型获得了子能带结构.     

Monte Carlo study of strained GermaniumNanoscale bulk pMOSFETs

In this paper, we perform fullband Monte Carlo simulations of nanoscale strained Ge bulk pMOSFETs with compressive strain in the strained Ge layer. We consider transport in the presence of phonon, ionized impurity, surface roughness scattering and impact ionization. Quantum confinement in the inversion layer is taken into account in the form of a modified potential. Strained Gedevices gave higher drive current when compared with unstrained Ge devices for the device structures studied.     

A latch phenomenon in buried N-body SOI NMOSFET's

The authors show that a snapback effect resulting in a latching can exist in a buried N-body NMOS device on silicon-on-insulator (SOI). Using numerical simulations, it is demonstrated that when V_GS is less than the flat-band voltage and after triggering, this kind of device behaves as a floating-base n-p-n bipolar transistor, the base hole density of which is controlled by an inversion layer instead of the usual base doping. The latch phenomenon results from the combination of this parasitic quasi-bipolar device, a back surface NMOS transistor, and impact ionization current     

A mobility model for submicrometer MOSFET device simulations

This paper describes a mobility model for submicrometer MOSFET device simulations. The model includes the quantum effects of electrons in the inversion layer proposed by Schwarz et al. By comparison with experimental data from scaled MOSFET's, the limitation of Yamaguchi's model in submicrometer device simulations is implied, while the quantum channel broadening effects have been proven significant in turn. This model can predict the current-voltage characteristics within 5- percent accuracy for scaled MOSFET's down to 0.5 µm.     

The subthreshold behavior of SOS MOST's

MOST subthreshold behavior is of importance in many modern dynamic and very-low-power circuits. SOS MOST's exhibit quite generally a lower transconductance than bulk Si MOST's. Comparison between SOS and bulk Si MOST's is made on the basis of a simple model in the weak inversion region. Experiments with n-and p-channel SOS MOST's fabricated with epi Si layer thicknesses ranging from 0.1 to 3 µm confirm the predicted decrease of transconductance in weak inversion with decreasing thickness. Quantitative agreement between model and experience is obtained if a ∼350-Å thick nonconductive Si layer near the Si-sapphire interface is assumed. A transconductance jump observed for epi Si thickness equal to the surface maximum depletion width has not yet been explained. Further experiments including fabrication process, back-gate voltage measurements, and device dimensions were performed in order to investigate the low-transconductance origin. It is concluded that the only relevant parameters are the epi Si layer thickness and the high density of fast states at the Si-sapphire interface.     

On the condition of strong inversion and terminal voltages in MOS structures with nonuniform and degenerate doping

An expression is derived which relates the potentials at the surface and the depletion layer edge at the onset of strong inversion to the applied voltage between source and bulk of an MOS structure. The expression is valid for degenerate and nonuniformly doped substrates. A new definition of strong inversion is proposed which reduces to the definition given by Doucet and van de Wiele under nondegenerate conditions. A simplified structure is considered which allows the MOS device to be analyzed using a one-dimensional model. The role of metal-semiconductor contacts and the assumptions involved in the analysis are discussed.     

A semi-empirical model of surface scattering for Monte Carlosimulation of silicon n-MOSFETs

A semi-empirical model of surface scattering for Monte Carlo simulation of electrons in the silicon inversion layer at 300 K is proposed. The model compares favorably with different sets of experimental electron effective mobility data over a wide range of normal electric fields, channel impurity concentrations, and substrate bias. Comparisons between Monte Carlo and drift-diffusion simulations show that the model is able to correctly predict the device termination currents in the regime where nonequilibrium transport effects are negligible. It is expected therefore that at small device lengths the Monte Carlo predictions are also quantitatively correct     

Frequency response of charge transfer in MOS inversion layers

The dynamics of charge transfer from a reservoir into an MOS inversion layer, which limits the frequency response of an MOS transistor or a charge-coupled device, is investigated. Using Berman and Kerr's model of space-charge capacitance in the semiconductor, a small-signal distributed model is developed for an MOS structure which transfers charge in an inversion channel due to a variation in the gate voltage. The dynamics of the charge transfer is characterized by a time constant which is determined by the length of the inversion channel and its mobility. Experimental data of gate capacitance vs frequency, taken from a test structure with a diffused source/drain well, are satisfactorily fitted by theoretical curves derived from the model. The channel mobility is precisely determined from the adjusted time constant. The influence of interface states on the capacitance-frequency relationship is also briefly discussed.     

Statistical variability in FinFET devices with intrinsic parameter fluctuations

High-κ/metal-gate and vertical channel transistors are well-known solutions to continue the device scaling. This work extensively estimates the influences of the intrinsic parameter fluctuations on nanoscale fin-type field-effect-transistors and circuits by using an experimentally validated three-dimensional device and coupled device-circuit simulations. The dominance fluctuation source in threshold voltage, gate capacitance, cut-off frequency, delay time, and power has been found. The emerging fluctuation source, workfunction fluctuation, shows significant impacts on DC characteristics; however, can be ignored in AC characteristics due to the screening effect of the inversion layer.