Guest Editorial: Special Issue on Embedded Multicore Applications and Optimization

Journal of Signal Processing Systems -     

SDH保护机制及混合网络结构下的实现方式

本文介绍了几种主要的SDH保护机制的实现原理与特点,以及在混合网络结构中几种保护机制的互连与互通应用。     

50 Years of CORDIC: Algorithms, Architectures, and Applications

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.     

Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis

Memory-intensive applications present unique challenges to an application-specific integrated circuit (ASIC) designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latencies, etc. The high potential of single-chip distributed logic-memory architectures in addressing many of these issues has been recognized in general-purpose computing, and more recently, in ASIC design. The high-level synthesis (HLS) techniques presented in this paper are motivated by the fact that many memory-intensive applications exhibit irregular array data access patterns. Synthesis should, therefore, be capable of determining a partitioned architecture, wherein array data and computations may have to be heterogeneously distributed for achieving the best performance speed-up. We use a combination of clustering and min-cut style partitioning techniques to yield distributed architectures, based on simulation profiling while considering various factors including data access locality, balanced workloads, inter-partition communication, etc. Our experiments with several benchmark applications show that the proposed techniques yielded two-way partitioned architectures that can achieve upto 2.1 x (average of 1.9 x) performance speed-up over conventional HLS solutions, while achieving upto 1.5 x (average of 1.4 x) performance speed-up over the best homogeneous partitioning solution feasible. At the same time, the reduction in the energy-delay product over conventional single-memory designs is upto 2.7 x (average of 2.0 x). A larger amount of partitioning makes further system performance improvement achievable at the cost of chip area.     

多芯光纤激光器的研究

阐述了多芯光纤的优点和结构,介绍了多芯光纤激光器达到大的输出功率的机理和同相位模式的选模和耦合原理,最后介绍了近年多芯光纤激光器的研究进展。     

新一代网络结构的研究

新一代网络是以数据网为核心的,融合了各种现有网络技术的集成网络,好的体系结构对网络技术的发展至关重要。对新一代网络结构的最新研究成果进行了介绍,主要介绍了Parlay,JAIN,国际软交换组织,多业务交换论坛等几家组织提出的一些新的观点和建议。     

基于多核防火墙的防病毒引擎设计与实现

提出了一种基于多核的防病毒引擎的设计模型,并根据此模型实现了一款包含防病毒引擎的防火墙,经过测试表明,此款多核防病毒引擎的实现与传统防病毒引擎相比性能优异,满足高性能网络安全的需要。该模型主要有以下几个特点：解决多核硬件本身的报文乱序的问题而造成的对AV引擎的影响,从而达到减少漏报的功能;在多核数据平面实现基于报文流的查找,不进行报文的拷贝而实现跨包查找病毒的功能。     

Toward Efficient Execution of RVC-CAL Dataflow Programs on Multicore Platforms

The increasing number of cores in System on Chips (SoC) has introduced challenges in software parallelization. As an answer to this, the dataflow programming model offers a concurrent and reusability promoting approach for describing applications. In this work, a runtime for executing Dataflow Process Networks (DPN) on multicore platforms is proposed. The main difference between this work and existing methods is letting the operating system perform Central processing unit (CPU) load-balancing freely, instead of limiting thread migration between processing cores through CPU affinity. The proposed runtime is benchmarked on desktop and server multicore platforms using five different applications from video coding and telecommunication domains. The results show that the proposed method offers significant improvements over the state-of-art, in terms of performance and reliability.     

未来互联网选路体系结构研究

文章认为可以通过身份、位置、选路、服务4个要素,对各种未来网络的体系结构进行分类和比较.基于这个观点,文章归纳了位置标志和身份标志分离,边缘网络和核心网络分离,以及全局位置标志、局部位置标志和身份标志分离的未来网络的体系结构,并提供了结构的分类和比较思路.     

Evaluation of Low-Power Computing when Operating on Subsets of Multicore Processors

Given the accelerated growth in tablet devices, smartphones, and netbooks, designers are faced with serious challenges to meet the needs of mobility in terms of battery life and form factor. It is vital to investigate how to deliver the best mobile experience to users while ensuring adequate levels of performance. In this paper, we present a power management evaluation of multi-core processor systems by comparing thermal power, battery life, and performance when running different types of workloads under a limited number of cores. To show the potential gains from a system power management perspective, we have assessed a mobile platform featuring the Second Generation Intel Core i5 processor, and tested it on a wide selection of workloads and benchmarks. Experimental results show significant thermal power reduction (up to 40 %) in a variety of scenarios, while system performance was sustained in most cases but sacrificed in a few other uncommon situations.     

异构多核处理器分支预测器研究与设计

为解决单核处理器时钟频率难以提高、处理器功耗逐渐增加等问题,文中提出了一种新型异构多核处理器的设计方案．该结构中增加了B--Cache结构和C--Core控制器,这种新型异构多核处理器避免了流水线因分支预测失误而flush,提高了整个处理器执行效率．     

OFDM技术应用浅析

介绍了OFDM技术的基本原理和一些实际应用,重点分析了OFDM在DTTB运用中的优势和发展变化,指出了设计和应用OFDM系统的几个关键点.     

一种多核系统可靠性加强的任务调度方法

 多核系统已经被广泛应用于各行各业,其稳定性和可靠性也越来越受到人们的关注.在分析了现有芯片可靠性模型的基础上,增加温度和工作负载对多核芯片可靠性的影响,建立了对多核系统的可靠性评估模型.该模型以处理器为依托,从指令到任务,逐层构建可靠性评估指标,以便于定量分析影响多核系统可靠性的因素.同时,以该模型为指导,设计了一种面向多核系统可靠性的任务调度方法,该方法通过对评估指标值的计算,选择评估指标值尽可能高的调度策略对多核系统中的任务进行调度,以减少由于芯片本身可靠性而导致的错误.通过模拟实验可以看出,该任务调度算法能有效减少系统的出错率45%左右,为系统的稳定运行提供了可靠的保证.     

基于英飞凌AURIX单片机的AUTOSAR多核操作系统的实现

文章概述了AUTOSAR和英飞凌AURIX系列单片机。该文在英飞凌AURIX TC275单片机硬件基础上,利用VECTOR公司Davinci工具构建了多核操作系统,并实现了多核操作系统中不同核间任务的运行,通过示波器上电平翻转情况测试多核操作系统是否成功实现。     

智能网与因特网互联方案的探讨

本文在介绍ＩＮ与Ｉｎｔｅｒｎｅｔ互联可支持哪些业务的基础上，重点对目前国际上正在讨论的两种方案进行了分析和探讨，最后，针对上述两种方案存在的缺陷，提出了一种新的互联方案。     

Charge Pump Architectures Based on Dynamic Gate Control of the Pass-Transistors

In this paper, we present two charge pump architectures for nonvolatile memories with dynamic biasing of the gate and the body voltages. By controlling the gate and the body voltage of each pass-transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the following with a negligible voltage drop and large conductivity. The charge pumps were fabricated in the ST 130-nm digital standard CMOS technology. Compared to conventional charge pumps, larger output voltage and better power efficiency are achieved still retaining a simple two-phase clocking scheme. Measurements performed on four-stage and eight-stage charge pumps are provided.      

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility,Speed and Complexity Trade-Offs

The design of Fast Fourier Transform (FFT) integrated architectures for System-on-Chip (SoC) telecom applications is addressed in this paper. After reviewing the FFT processing requirements of wireless and wired Orthogonal Frequency Division Multiplexing (OFDM) standards, including the emerging Multiple Input Multiple Output (MIMO) and OFDM Access (OFDMA) schemes, three FFT architectures are proposed: a fully parallel, a pipelined cascade and an in-place variable-size architecture, which offer different trade-offs among flexibility, processing speed and complexity. Silicon implementation results and comparisons with the state-of-the-art prove that each macrocell outperforms the known works for a target application. The fully parallel is optimized for throughput requirements up to several GSamples/s enabling Ultra-wideband (UWB) communications by using all channels foreseen in the standard. The pipelined cascade macrocell minimizes complexity for large size FFTs sustaining throughput up to 100 MSamples/s. The in-place variable-size FFT macrocell stands for its flexibility by allowing run-time reconfigurability required in OFDMA schemes while attaining the required throughput to support MIMO communications. The three architectures are also compared with common case-studies and target technology.