An On-Chip Sensor to Monitor NBTI Effects in SRAMs

The increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of Systems-on-Chip (SoCs). Therefore, SRAM’s robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena that degrades Nano-Scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI), which causes the memory cells aging. The main goal of this paper is to present a hardware-based approach able to monitor SRAMs’ aging during the SoC’s lifetime based on the insertion of On-Chip Aging Sensors (OCASs). In more detail, the proposed strategy is based on the connection of one OCAS to every SRAM column, each periodically monitoring write operations on the SRAM cells. It is important to note that in order to prevent the OCAS from aging and to reduce leakage power dissipation, the OCAS circuitry is powered-off during its idle periods. The proposed hardware-based approach has been evaluated throughout SPICE simulations using 65 nm CMOS technology and the results demonstrate the sensor’s capacity to detect early aging states and therefore, guaranteeing high SRAM reliability. To conclude, a complete analysis of the sensor’s overheads is presented.     

Dynamic Power Supply Current Testing for Open Defects in CMOS SRAMs

The detection of open defects in CMOS SRAM has been a time consuming process. This paper proposes a new dynamic power supply current testing method to detect open defects in CMOS SRAM cells. By monitoring a dynamic current pulse during a transition write operation or a read operation, open defects can be detected. In order to measure the dynamic power supply current pulse, a current monitoring circuit with low hardware overhead is developed. Using the sensor, the new testing method does not require any additional test sequence. The results show that the new test method is very efficient compared with other testing methods. Therefore, the new testing method is very attractive.     

NBTI Impact on RF Front End in Wireless Sensor Networks

In wireless sensor network （WSN）, the communication node is the heart of the whole system. Negative bias temperature instability （NBTI） is becoming one of the most important factors that decide the life time of node chips, especially with the feature size declining. In this paper, the NBTI impact on the front-end circuits in the WSN nodes is studied, such as voltage-controlled oscillator （VCO）, charge pump （CP）, low noise amplifier （LNA）, and even the whole transceiver system. The circuit level NBTI degeneration models are built for the key modules and the entire transceiver. It is shown that the phase noise of the VCO will be deteriorated, the current mismatch of the CP and the noise figure of the LNA will both be increased, and the sensitivity and the adjacent channel selectivity （ACS） will be depressed by NBTI. The conclusions are proved by simulation results using HJTC 0.18 μm technology.     

Impact of NBTI and HCI on PMOSFET threshold voltage drift

Negative bias temperature instability (NBTI) induced PMOSFET parameter degradation is a serious reliability concern in advanced analog and mixed signal technologies. In this paper, V_t-mismatch shift due to NBTI in a cascode current mirror is examined. The impact of NBTI and hot-carrier injection (HCI) on threshold voltage degradation and subsequent damage recovery during annealing is also studied. Finally the influence of channel length, gate voltage, drain voltage and damage recovery on conventional NBTI and HCI DC lifetime extrapolation is characterized with the impact on analog applications highlighted.     

Impact of NBTI on the temporal performance degradation of digital circuits

Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.     

Analysis of Resistive Open Defects in Drowsy SRAM Cells

New fault behaviors can emerge with the introduction of a drowsy mode to SRAMs. In this work, we show that, in addition to the data-retention faults that can occur during the drowsy mode, open defects in SRAM cells can also result in new fault behaviors when a memory is accessed immediately after wake-up. We first describe these new read-after-drowsy (RAD) fault behaviors and derive their corresponding fault primitives (FPs). Then, we propose a new March test, called March RAD, by inserting drowsy operations to a traditional test algorithm. Finally, the impact of the standby supply voltage on triggering the drowsy faults in SRAM cells is investigated. It is shown that, as the supply voltage is reduced in the drowsy mode to further cut down leakage, open defects with a parasitic resistance as small as 100 K Ω begin to cause faults.     

Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

Negative Bias Temperature Instability (NBTI) in pMOS transistors has become a major reliability concern in the state-of-the art digital circuit design. This paper discusses the effects of NBTI on 32 nm technology high fan-in dynamic OR gate, which is widely used in high-performance circuits. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG), are analyzed in the presence of NBTI degradation. We have shown the degradation in the output inverter pMOS transistor of the domino gate has a dominant impact on the delay in comparison with the keeper impact. Based on this analysis we have proposed that upsizing just the output inverter pMOS transistor can compensate for the NBTI degradation. Moreover, the impact of tuning the duty cycle of the clock has been investigated. It has been shown that although the keeper and the precharge transistors experience more NBTI degradation by increasing the low level in the clock signal, the total performance of the circuit will improve. We have also proposed an adaptive compensation technique based on Forward Body Biasing (FBB), to recover the performance of the aged circuit.     

Impact of NBTI induced variations on delay locked loop multi-phase clock generator

Negative bias temperature instability (NBTI) is a serious reliability concern for both analog and digital CMOS VLSI circuits. The shift in threshold voltage and reduction in drain current due to NBTI in p-channel MOSFETs are time, bias and temperature dependent. The degradation of the PMOS at any critical nodes in the circuit leads to the failure of the circuit immediately or in few months/year. The Delay-Locked-Loop (DLL) which is used as multi-phase clock generator for microprocessors, frequency synthesizers, time-to-digital converter (TDC) etc. reduces the phase error between output and reference clock until it is locked. The delay variations due to process, voltage and temperature fluctuations are governed by its feedback system. At start-up, the phase shift of the output clock should lie between 0.5 and 1.5 times the time period of the reference clock to achieve regular locking. The deviations from the above criteria due to NBTI degradation directly affect the control system and lead to erroneous locking. The NBTI-induced time-dependent variation in PMOS of the delay stage in voltage-controlled delay line (VCDL) of DLL affects the delay in each stage of VCDL and propagates as phase error to the output clock. This paper analyzes the impact of NBTI-induced time-dependent variations in Delay-Locked-Loop (DLL) based clock generators for the first time. The DLL is designed with 180 nm technologies with working frequency range from 75 MHz to 220 MHz. The time dependent variations in VCDL, the most sensitive blocks of DLL, are analyzed. It is observed that these time-dependent variations increase the phase error and the working of DLL is severely affected at the rearmost end of frequency range. The output clock gets deviated and observed to be locked late after π/2 or π radians from the nominal lock. It is essential to prevent DLL locking to an incorrect delay or false lock and to bring the output clock back to the correct position. An adaptive body bias circuit is proposed in this paper to reduce the impact of NBTI degradation and thereby to prevent erroneous locking in DLL.     

Ultrafast Measurement on NBTI

We combine customary pulsed $I$– $V$ setup with a simple linear drain–current correction method to provide a possible standard for NBTI characterization. The method is implemented using standard equipment and yet is able to achieve sub-100-ns delay, the shortest reported to date for a wafer-level setup. Unlike the ramped-voltage method for which synchronization of the gate and drain waveforms is critical, relative delay between the gate and drain signals is not a concern in our case since measurement is made during quasi-steady state. For the present setup, gate and drain signals are shown to “stabilize” after $sim!hbox{50}$ ns (upon switching) for a gate capacitive load of 1.5 pF (equivalent to $sim!hbox{80} $ devices used in this letter), rendering parallel testing possible using a single gate voltage source. Extension of the method for direct threshold voltage extraction by the constant subthreshold drain current approach is also discussed.      

Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer

This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the synchronizer, and HSPICE is used to perform circuit analysis. The major purpose of this analysis is to find all possible faults that might occur in the synchronizer. Simulation results demonstrate that bridging fault effects of the synchronizer depend on fault location, bridging resistance value, the input signal (rising and falling), and the time of input signal application. The issues of bridging fault behavior under the consideration of process variation, and the relationship between bridging faults and the synchronizer failure mechanisms are also discussed.     

Defects and Resistive Switching of Zinc Oxide Nanorods with Copper Addition Grown by Hydrothermal Method

Vertically aligned zinc oxide (ZnO) nanorods (NRs) were hydrothermally synthesized from 0.1 M zinc acetate solution on ZnO-seeded Si(100) substrates. ZnO NRs with copper addition were also synthesized by introducing copper acetate into the zinc acetate solution to investigate the effects of copper addition on the growth and resistive switching of the ZnO nanorods. The ZnO NRs had hexagonal wurtzite structure with preferential c-axis orientation. Copper was mainly present as copper oxide (CuO) secondary phase which produces many visible defects, and the lattice fringes of the ZnO NRs are thereby damaged. Copper addition quenches the ultraviolet emission of the ZnO NRs but enhances their green emission. Additionally, copper addition shifts the Zn 2p and O 1s peaks of the x-ray photoelectron spectra towards lower binding energy, which may result from an increase of oxygen vacancies. ZnO NRs with and without copper addition exhibit reversible bipolar resistive switching. The copper addition shrinks the deviations of programming voltages, with a decrease in the minimal set voltage and an increase in the minimal reset voltage, which can probably be attributed to the introduced oxygen vacancies and the copper-related defects.     

Instruction Fetch Energy Reduction with Biased SRAMs

Especially in programmable processors, energy consumption of integrated memories can become a limiting design factor due to thermal dissipation power constraints and limited battery capacity. Consequently, contemporary improvement efforts on memory technologies are focusing more on the energy-efficiency aspects, which has resulted in biased CMOS SRAM cells that increase energy efficiency by favoring one logical value over another. In this paper, xor-masking, a method for exploiting such contemporary low power SRAM memories is proposed to improve the energy-efficiency of instruction fetching. Xor-masking utilizes static program analysis statistics to produce optimal encoding masks to reduce the occurrence of the more energy consuming instruction bit values in the fetched instructions. The method is evaluated on LatticeMico32, a small RISC core popular in ultra low power designs, and on a wide instruction word high performance low power DSP. Compared to the previous “bus invert” technique typically used with similar SRAMs, the proposed method reduces instruction read energy consumption of the LatticeMico32 by up to 13% and 38% on the DSP core.     

NBTI model development with regression analysis

In industry, negative bias temperature instability (NBTI) mechanism degradation models are derived from regression analysis of stress data. The model exponents vary for different technologies and manufacturers. We will show that limited sampling (using only one lot) and the misapplication of regression analysis are major contributors to the variation in model coefficients. Linearizing a nonlinear equation by taking logarithms will give more emphasis to smaller values and less to larger values.     

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

The embedded Flash (eFlash) technology can be subject to defects creating functional faults. In this paper, we first generalize the electrical model of the ATMEL TSTAC™ eFlash memory technology proposed in [10]. The model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model is validated by means of simulations and comparisons with ATMEL silicon data. Then, we present a complete analysis of actual resistive defects (open and short) that may affect the ATMEL TSTAC™ eFlash array by considering the proposed model on a hypothetical 4 × 4 array. This analysis highlights the interest of the proposed model to provide a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing.     

不同规模SRAM辐射损伤效应的研究

通过对ETC公司的商用256 kb和1 Mb CMOS SRAM器件在不同偏置条件(包括静态偏置和动态读写偏置)下进行电离辐射效应的研究,获得了SRAM器件电气参数和功能出错数随总剂量的响应关系.实验结果表明,功耗电流随累积剂量的增加变化明显,可以作为表征SRAM辐射损伤的敏感参数,但功能出错数与功耗电流的变化不同步,与功耗电流没有必然联系,原因是功能出错主要由栅氧阈值电压负漂引起,而功耗电流的增加主要由栅氧和场氧阈值电压负漂造成的漏电引起.     

材料内部热阻热容型缺陷的红外检测模拟研究

在数值传热学的基础上,从理论上对材料内部热阻性、热容性两类缺陷的平板进行了二维温度场的数值模拟,并根据模拟的温度场,对缺陷进行了模拟再现研究。研究结果表明,通过红外温度检测及模拟温度场,可以有效地检测内部缺陷的性质及大小,从而预防和避免事故发生。     

深亚微米p+栅pMOSFET中NBTI效应及氮在其中的作用

研究了p+栅pMOSFET中的NBTI效应.通过实验分析了NBTI应力后器件特性及典型参数的退化,研究了氮化栅氧中氮对NBTI效应的作用,并给出了栅氧中的氮对NBTI效应影响的可能机制,即栅氧中氮形成的Si-N键不易被分解,但栅氧中的氮提供了H+的陷阱中心,导致NBTI效应中氧化层正固定电荷的增加,其总体效果表现为氮对NBTI效应退化影响的增加.     

深亚微米p+栅pMOSFET中NBTI效应及氮在其中的作用

研究了p+栅pMOSFET中的NBTI效应．通过实验分析了NBTI应力后器件特性及典型参数的退化，研究了氮化栅氧中氮对NBTI效应的作用，并给出了栅氧中的氮对NBTI效应影响的可能机制，即栅氧中氮形成的Si—N键不易被分解，但栅氧中的氮提供了H＋的陷阱中心，导致NBTI效应中氧化层正固定电荷的增加，其总体效果表现为氮对NBTI效应退化影响的增加．     

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis

Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of circuit speed over a long period of time. The effectiveness of our method is comprehensively demonstrated with the International Symposium on Circuits and Systems (ISCAS) benchmarks and a 65-nm industrial design. Furthermore, we extract the following key design insights for reliable circuit design under NBTI effect, including: 1) During dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; 2) There is an optimum supply voltage that leads to the minimum of circuit performance degradation; circuit degradation rate actually goes up if supply voltage is lower than the optimum value; 3) Circuit performance degradation due to NBTI is highly sensitive to input vectors. The difference in delay degradation is up to 5$times $ for various static and dynamic operations. Finally, we examine the interaction between NBTI effect, and process and design uncertainty in realistic conditions.