Fast acquisition clock and data recovery circuit with low jitter

This paper presents a half-rate clock and data recovery circuit (CDR)that combines the fast acquisition of a phase selection (PS) delay-locked loop (DLL) with the low jitter of a phase-locked loop (PLL). The PLL acquisition time improves considerably with use of a phase frequency magnitude detector(PFMD) that feeds back an estimate of the magnitude of the frequency difference in addition to the sign. Measurements in 0.5/spl mu/m CMOS technology show operation up to 700 Mb/s, a 7% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps after the PLL acquires lock. With a phase frequency detector (PFD), the PLL locks in about 700 ns from an initial frequency difference of 7%. Measurements using a PFMD show the 700 ns PLL acquisition time is reduced on average by about a factor of 5 to 140 ns from an initial 7% frequency difference. The power dissipation is 300mW.     

Self-correcting clock recovery circuit with improved jitter performance

In the letter we present a new clock recovery circuit with self-correction of the position of the retiming clock, which shows the reduction of the output jitter by deleting the phase difference of ? radians in the output of the phase detector existing in Hogge's scheme.     

Low power clock recovery circuit for passive HF RFID tag

A low power clock recovery circuit for passive HF RFID tag is presented. The proposed clock recovery circuit, based on the architecture of Phase Locked Loop (PLL), is used to generate a stable system clock when communication occurs from interrogator to tag with 100% ASK modulation. An envelope detector is designed to detect the incident power from interrogator and control the operating state of the proposed clock recovery circuit. Loop bandwidth of PLL circuits is minimized to reduce the frequency deviation when operating in frequency maintaining state. Furthermore, an initialization circuit for loop filter is also used to speed up locking during initial system power-on-reset. Prototype chips have been fabricated in 0.35 μm 2P4M CMOS technology. A total current consumption of 3 μA has been achieved in the frequency maintaining state. Measurement results show that, when communication occurs from interrogator to tag with 100% ASK modulation, clock recovery circuit generates a stable and consecutive system clock and has an inevitable frequency derivation of 7.5% when operating in frequency maintaining state.     

Design and fabrication of waveguide-based chip-to-chip optical interconnection network on printed circuit boards

A waveguide-based chip-to-chip optical interconnection network on printed circuit board (PCB) was designed and fabricated, and experiments confirmed that the data rate in each channel could reach above 3.125 Gbit/s and the bit error rate (BER) could be up to 1.27×10-18, which would be a good solution to solve the communication bottlenecks between high-speed very large scale integration chips. Besides, the whole design and fabrication of optical interconnection network on printed circuit board has the advantages of high reliable, low cost and ease of manufacture.     

一种快速同步的时钟数据恢复电路的设计实现

时钟数据恢复(CDR)电路是通信传输设备中的重要部分,对于突发式的接收,基于锁相环的传统的CDR往往不能满足其快速同步的要求.对此,文章采用过采样方式基于FPGA设计实现了一种全数字化的155.52Mb/s下的CDR电路.理论分析、仿真和实验测试结果表明,该CDR电路可以有效地对相位变化实现快速同步,有很大的捕捉范围,且系统较锁相环便于集成.     

高速时钟与数据恢复电路技术研究

本文根据数据恢复时,本地时钟与输入数据之间的相位关系及其实现方式的不同,将高速时钟与数据恢复(CDR,Clock and Data Recovery)电路技术分为三类,也即前馈相位跟踪型,反馈相位跟踪型,以及盲过采样型。进而又分别对每一类型进行了细分并分别进行了深入的剖析和比较。最后又给出了不同应用环境下,CDR技术的选择策略,并指出了CDR技术的发展趋势。本文通过对高速CDR技术详尽而又深刻的分析比较,勾勒出了一个高速CDR技术的关系及发展演化图,使读者能够对现存的高速CDR技术及其发展趋势有一个前面而又清晰的认识。     

2.5 Gbit/s clock and data recovery circuit IC using novelduplicated PLL technique

A 2.5 Gbit/s monolithic clock and data recovery integrated circuit (CDR IC) based on a novel duplicated phase-locked loop (PLL) technique has been fabricated using 0.5 μm Si bipolar technology. This CDR IC operates more stably in that it can tolerate greater variations in temperature and supply voltage while continuing to meet the specifications for jitter characteristics stipulated in the ITU-T recommendations     

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.     

A monolithic 156 Mb/s clock and data recovery PLL circuit using thesample-and-hold technique

The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 2²³-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor     

基于FPGA的高速时钟数据恢复电路的实现

介绍了一种利用输出时钟在具有不同相位的时钟信号之间进行切换实现高速时钟恢复电路的方法。利用Altera公司Quartus软件提供的修改逻辑单元和逻辑块锁定及插入buffer的方法,消除了时钟切换产生的毛刺,弥补了不同相位时钟由于不同的传输延迟而造成的相位偏移。设计的电路实现了数字光端机要求的204．8MHz的工作频率。同时,分析了决定该电路工作频率的主要因素,通过仿真验证使用EP3C10El44C7芯片最高工作频率可以达到400MHz。     

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit

A 155.52 Mbps-3.125 Gbps continuous-rate clock and data recovery (CDR) circuit using the full-rate bang-bang phase detector is presented. A frequency detector is proposed to eliminate the harmonic locking problem even with a wide range of data rates and its theoretical analysis is also discussed. A quadrature divider is also presented to generate the clocks with accurate quadrature phases. This CDR circuit has been realized in a 0.18-/spl mu/m CMOS process and its die area is 1.1/spl times/0.8 mm/sup 2/. It consumes 95 mW at the highest bit rate of 3.125 Gbps. It can recover the NRZ data of a 2/sup 31/-1 PRBS with the bit rate ranging from 155.52 Mbps to 3.125Gbps for the incremental frequency acquisition and the NRZ data of a 2/sup 7/-1 PRBS for the decremental frequency acquisition. All the measured bit error rates are less than 10/sup -12/.     

10Gb/s突发模式时钟数据恢复电路设计

突发模式的时钟数据恢复是10G EPON系统的关键技术之一。本文介绍了一种基于XNOR/XOR门的振荡器,分析了其工作原理与性能,以此为基础设计了半速率突发时钟恢复电路。设计采用SMIC 0.13?m CMOS工艺进行了流片验证,芯片面积为675?m ? 625?m。测试结果表明,该电路可以即时的实现10Gbit/s的突发数据恢复,恢复出的时钟数据符合IEEE 802.3av标准,锁定时间小于5bit。     

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2⁷-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm²     

时钟提取与抖动衰减数字锁相环设计研究

文章简要介绍了数字锁相环(DPLL)的工作原理,重点提出了用于V5接口芯片中的时钟提取锁相环和抖动衰减锁相环的设计,并对其进行了分析．     

用于移动支付的高精度高灵敏度时钟恢复电路

介绍了一个应用在移动支付系统里的全集成载波时钟恢复电路。它由一个采样检测模块和一个电荷泵锁相环组成。与传统13.56MHz标签里的时钟恢复电路相比,这个电路能够从开关键控信号里恢复高精度的连续载波时钟。整个芯片由0.18μm EEPROM CMOS工艺制造,工作电压为1.5V。实验结果表明该电路恢复频率的偏移为0.34%,灵敏度为8mV。     

High-precision high-sensitivity clock recovery circuit for a mobile payment application

This paper presents a fully integrated carrier clock recovery circuit for a mobile payment application. The architecture is based on a sampling-detection module and a charge pump phase locked loop.Compared with clock recovery in conventional 13.56 MHz transponders,this circuit can recover a high-precision consecutive carrier clock from the on/off keying(OOK) signal sent by interrogators.Fabricated by a SMIC 0.18-μm EEPROM CMOS process,this chip works from a single power supply as low as 1.5 V.Measurement results show that this circuit provides 0.34%frequency deviation and 8 mV sensitivity.     

An analog PLL-based clock and data recovery circuit with high inputjitter tolerance

A clock and data recovery circuit for a T1 network is described. A fully integrated phase-locked loop (PLL) extracts the carrier signal embedded in the data. Two trimming DACs simultaneously bring the VCO center frequency and the PLL closed-loop bandwidth to their specified values. A triple sampler captures the jittering data and aligns them with the recovered clock. The input jitter of this circuit is three times more than previously reported PLL-based circuits     

The jitter time-stamp approach for clock recovery of real-timevariable bit-rate traffic

When multimedia streams arrive at the receiver, their temporal relationships may be distorted due to jitter. Assuming the media stream is packetized, the jitter is then the packet's arrival time deviation from its expected arrival time. There are various ways to reduce jitter, which include synchronization at the application layer, or synchronization at the asynchronous transfer mode (ATM) adaptation layer (AAL). The new source rate recovery scheme called jitter time-stamp (JTS) provides synchronization at the ATM adaptation layer 2 (AAL2) which is used to carry variable bit-rate traffic such as compressed voice and video. JTS is implemented, and experiments have shown that it is able to recover the source rate     

Low-jitter design method based on Wn-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

A low-jitter design method based on vn-domain jitter analysis for the clock and data recovery (CDR) ICs using the linear phase-locked loop (PLL) is proposed. Using this method, the loop parameters of the PLL can be optimised, which makes it possible to design the CDR IC for various targets.     

A self correcting clock recovery circuit

Conventional approaches to the problem of extracting clock from NRZ data do not automatically hold the clock in the center of the data eye. Other means must be used to keep the clock properly centered in the eye at the decision flip-flop. A new approach to the problem is described. The circuit is both simple and self correcting.