边做边学数字电路（五）

（续上期）本期我们走出数字电路的“单身世界”，开始给它们成立“家庭”，也就是把不同的单逻辑电路进行组合，比如组成“与非门、或非门”等等，即组合逻辑门。组合逻辑可执行的逻辑功能更多!由于克服了很多单逻辑电路固有的缺点，因此在实际应用中采用组合逻辑门的电路更多。为了使大家比较容易入门，咱们就从最常见的组合门“与非门”开始学习。在小家电产品中最常采用的CD4011就是一个与非门集成电路。[第一段]     

GPIB接口的CPLD实现

论述了基于CPLD的GPIB接口设计。GPIB接口采用ALTERA公司的EPM7128系列芯片实现。由于该芯片的价格远低于GPIB接口芯片,使得制作带有GPIB接口智能仪器的成本大幅度降低。又由于EPT7128芯片的门电路十分丰富,在智能仪器的设计过程中还可将分离的逻辑电路集成于统一芯片,使智能仪器的设计得到简化,可靠性得到提高。     

基于DSP的无位置传感器永磁同步电机调速系统

利用TMS320F240 DSP芯片设计了一套无位置传感器永磁同步电机调速系统，详细介绍了电机无位置传感器触发逻辑电路的设计，实验结果表明该系统的可行性和可靠性。     

同步时序逻辑电路设计基础

介绍了时序逻辑电路的分析和设计方法，使读者在了解了组合逻辑电路设计的基础上，了解基本触发器主从触发器和边沿触发器原理，能够分析，设计以触发器为核心元件，且与电路初态有关的时序逻辑电路。     

多数决逻辑门及其应用

在数字系统设计与制造中,通常采用与门族、或门族及与或非门族等构成各种大型逻辑网络。本文介绍一种功能更为全面的多数决逻辑门及其应用,多数决逻辑门的应用特点是组成各种逻辑电路的灵活性强,尤其在识别装置和大噪声环境中,采用多数决逻辑门可以提高数字系统的可靠性和容错能力。目前运用CMOS逻辑结构制成的5个输入端的多数决逻     

夏新照相手机DA8原理与维修

该手机逻辑电路采用了美国AD系列芯片组合，如音频ICAD6521、CPUAD6522。由AD6522、AD6521及电源IC MAX1868、存储器共同构成逻辑系统，对整机进行各种控制。     

基于DSP的无位置传感器永磁同步电机调速系统

利用TMS32 0F2 4 0DSP芯片设计了一套无位置传感器永磁同步电机调速系统 ,详细介绍了电机无位置传感器触发逻辑电路的设计 ,实验结果表明该系统的可行性和可靠性。     

三星N288逻辑电路完全维修——检修思路与实战经验篇

三星N288手机采用飞利浦公司生产的VP40575ARM作为逻辑芯片，该芯片还被应用在三星A288、N188、T108等型号手机上。VP40575内置音频处理、卡控制及其他接口电路。该芯片工作不正常会引起手机不开机、无信号、不认卡、难发射和通话不正常等故障，下面就以三星N288为例介绍一下以VP40575作为核心芯片手机的逻辑电路的维修。     

基于FPGA的数字视频转换接口的设计与实现

本文详细介绍了基于FPGA EP2C35F672的数字视频转换接口的设计及实现方法。重点描述了系统硬件的设计以及FPGA内部逻辑电路的设计,包括串转并、隔行变逐行和颜色空间转换等模块。实现了DVD播放器输出的模拟视频信号通过ADV7181电视解码芯片解码后,在VGA显示器上播放的功能。     

三值与非门及四态门开关电路的研究

采用双极型晶体管设计的三值TTL与非门及四态门均属于开关电路．这类门电路可用于构成三值组合逻辑电路和时序逻辑电路，也可以和DYL系列电路配合使用．     

Power·delay product in COSMOS logic circuits

In this simulation work, we use COSMOS logic devices—a novel single gate CMOS architecture recently announced [1]—in multi-input logic gates, assessing its performance in terms of power·delay product. We consider three different multi-input logic circuits: a two-input NOR gate, a three-input NOR gate, and a three-input composite NOR/NAND (NORAND) gate. For this power·delay analysis, the transient TCAD simulations are employed in a mixed-mode approach where circuit and device simulations are coupled together, culminating in the delay response of the circuits as well as the static/dynamic current components. The analysis shows that all circuits, except the 3-input NOR gate, has acceptable characteristics at low-power applications and static leakage limits all COSMOS circuits at high-bias conditions.     

Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates

An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency. If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley & Sons, Ltd.     

Static and dynamic characteristics of dual gate organic TFT based NAND and NOR circuits

This research paper analyzes the static and dynamic behavior of dual-gate organic thin film transistors (DG-OTFTs) based universal logic gates using the Atlas 2-D numerical device simulator. The electrical characteristics and performance parameters of pentacene based DG-OTFT is evaluated and verified with respect to the reported experimental results. The NAND and NOR logic gate circuits are realized using \(p\) -type designs in diode-load logic (DLL) and zero- \(V_{gs}\) -load logic (ZVLL). The results show that the logic functions in ZVLL configuration outperforms the DLL ones mainly in terms of noise margin, gain and voltage swing; however, there is a trade-off in terms of speed. The ZVLL NAND gate demonstrates an increment of 16 and 32 % in voltage swing and noise margin, respectively in comparison to the DLL one. Besides this, the gain also increases by 1.5 times in ZVLL mode. On the contrary, the DLL configuration demonstrates a significant reduction of 64 % in the propagation delay in comparison to the ZVLL. Similarly, NOR gate shows an increment of 24 and 30 % in voltage swing and noise margin, respectively under ZVLL configuration. However, the propagation delay for DLL NOR configuration is one-fourth of that of its ZVLL counterpart.     

Top-down design process for gate-level combinational logic design

A pedagogical process for designing gate-level combinational logic circuits is described. The process can be used for either combinational logic circuits or the combinational logic sections of sequential logic circuits. Positive logic signals (active high signals) as well as negative logic signals (active low signals) can be used in the design process. The top-down design process allows the student to draw functional logic diagrams in a rather routine manner using the positive logic convention, or the direct polarity convention. After obtaining functional logic diagrams, realizable logic diagrams can be easily obtained using any of the common off-the-shelf gate types including AND, OR, NAND, and NOR elements with appropriate inverter symbols. The advantage of the top-down design process is that students can very easily understand and implement gate-level combinational logic functions. Examples are provided to illustrate the top-down design process in teaching combinational logic design     

集成门极换流晶闸管门极驱动电路

介绍了集成门极换流晶闸管(IGCT)的基本结构,它同时拥有晶体管的关断特性和晶闸管的开通特性,是一种理想的兆瓦级中高压半导体开关器件.IGCT必须结合集成门极驱动电路才能完成硬开通和硬关断,因此门极驱动电路的性能将直接影响器件性能的优劣.具体设计了630A/4500V逆导GCT的驱动电路,并分析了驱动电路的要求和设计原理.     

ECL I/O buffers for BiCMOS integrated systems: a tutorial overview

In this paper we describe the methodology for the design and layout of fast BiCMOS ECL (emitter-couped logic) I/O buffers. Principles of ECL circuit operation are described with emphasis on the NOR/OR gate and the bandgap voltage reference. A comparison of ECL 10 K and 100 K logic families is presented as well as complete designs for an input and output buffer. The pad macros are temperature- and supply-voltage-compensated and have nominal rise and fall times of 400 ps     

Flash memory under cosmic and alpha irradiation

Neutron and proton irradiation to simulate cosmic ray jeopardy were used to establish that NOR Flash memory (conventional floating polySi gate or ONO floating gate MirrorBit) soft error failure rate (cross section) is 3-5 orders of magnitude better than SRAM. Flash memory soft error rate for a given dose of alpha particle irradiation is much less than for the same dose from simulated cosmic rays.     

Investigating the optical NOR gate using plasmonic nanorods

In this paper, a coherent perfect absorption‐type NOR gate based on plasmonic nano particles is proposed. It consists of two plasmonic nanorod arrays on top of two serial arms with quartz substrate. The operation principle is based on the absorbable formation of a conductive path in the dielectric layer of a plasmonic nanoparticle waveguide. Because the coherent perfect absorption efficiency depends strongly on the number of plasmonic nanorods and the locations of nanorods, an efficient binary optimization method based the Particle Swarm Optimization algorithm is used to design an optimized array of the plasmonic nanorods in order to achieve the maximum absorption coefficient in the ‘off’ state and the minimum absorption coefficient in the ‘on’ state. In Binary Particle Swarm Optimization, a group of birds consists a matrix with binary entries, control the presence (‘1’) or the absence (‘0’) of nanorods in the array. Copyright © 2016 John Wiley & Sons, Ltd.     

Parallel Operation Techniques of GTO Inverter Sets for Large AC Motor Drives

Techniques are presented for using a high-power GTO in a PWM inverter and operating inverter sets in parallel to increase the inverter equipment capacity. The high-power GTO has both a very large turn-off gate current and turn-on gate current for overdrive. It is best to employ an isolation pulse transformer for current amplification as the gate circuit. Also, the high-power GTO, which has a relatively small nonrepetitive controllable current compared with that of a medium- or low-power GTO, in principle can be protected effectively against short circuit faults using fuses. In parallel set operation, the inverter equipment has four typical behavior patterns which arise from differences in GTO switching characteristics. Of these, the behavior pattern in which the current balance is optimized is explained. In addition, the method for designing an interphase reactor as a current balancer and the combination region of GTO characteristics have been given. By means of a parallel set operation test, it has been confirmed that a current unbalance can be suppressed to below ten percent of the peak load current.     

Parametric analysis in the design of technological electron beam guns

A method of designing electron guns based on the method of parametric analysis and optimization is offered. The criteria of selection of variable parameters—the radius of the spherical surface of the gate electrode and the position of the center of the sphere with respect to the cathode—have been justified. It has been proven that taking due account of the technical limitations of materials and the chosen design allows reducing the task of designing the electron gun to the classical optimization problem. An example of calculating the characteristics of the prototype electron gun using the proposed method is given. Analysis of the results of computational experiments has allowed recommendations to be worked out for the developers of welding electron beam guns in the form of parametric dependences and design algorithms.