High-speed monolithically integrated silicon photoreceivers fabricated in 130-nm CMOS technology

A complementary metal-oxide-semiconductor (CMOS) monolithically integrated photoreceiver is presented. The circuit was fabricated in a 130-nm unmodified CMOS process flow on 2-/spl mu/m-thick silicon-on-insulator substrates. The receiver operated at 8 Gb/s with 2-dBm average input optical power and a bit error rate of less than 10/sup -9/. The integrated lateral p-i-n photodetector was simultaneously realized with the amplifier and had a responsivity of 0.07 A/W at 850 nm. The measured receiver sensitivities at 5, 3.125, 2, and 1 Gb/s, were -10.9, -15.4, -16.5, and -19 dBm, respectively. A 3-V single-supply operation was possible at bit rates up to 3.125 Gb/s. The transimpedance gain of the receivers was in the range 53.4-31 dB/spl Omega/. The circuit dissipated total power between 10 mW and 35 mW, depending on the design.     

37-GHz bandwidth monolithically integrated InP HBT/evanescently coupled photodiode

In this letter, we demonstrate a monolithically integrated optoelectronic integrated circuit (OEIC) for 1.55-/spl mu/m wavelength application. The presented OEIC consists of an evanescently coupled photodiode (ECPD) and a single-stage common-base InP-InGaAs heterojunction bipolar transistor (HBT) amplifier. The guide structure was grown first by metal-organic chemical vapor deposition and pin/HBT was then regrown by molecular beam epitaxy. The ECPD exhibits a responsivity of 0.3 A/W and a -3-dB electrical bandwidth of 30 GHz. The photoreceiver demonstrates a -3-dB electrical bandwidth of 37 GHz with a transimpedance gain of 32 dB/spl middot//spl Omega/. This is, to our knowledge, the first ECPD/HBT ever reported for a monolithically integrated OEIC.     

A thyristor-based photoreceiver based on the dual-channel double-heterostructure optoelectronic switch

A new approach to photoreceiver design is described based on the functionality of an optoelectronic thyristor. The receiver eliminates the transimpedance amplifier and the decision circuit by utilizing the internal gain of the thyristor and its nonlinear thresholding property. The sensitivity is determined by the shot noise on the input signal to be 360 photons per bit at a bit-error rate of 10/sup -9/. The speed of the photoreceiver is determined by the switching times of the thyristor. An output voltage signal from 0 to 1.5 V is obtained with switch on and off times of 12.5 ps and input photocurrent densities of 10/sup 4/ A/cm/sup 2/. The switch off time is equally as fast as the switch on due to the absence of stored charge in the modulation doped structure. The key to the high speed is the utilization of the third and fourth terminal contacts to the thyristor and the integration of the biasing transistors, which control the switching currents. An input optical signal of 0.5 mW will achieve this bandwidth in a device size of 0.2 /spl mu/m/spl times/12.5 /spl mu/m.     

A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-/spl mu/m CMOS

A 24-GHz +14.5-dBm fully integrated power amplifier with on-chip 50-/spl Omega/ input and output matching is demonstrated in 0.18-/spl mu/m CMOS. The use of substrate-shielded coplanar waveguide structures for matching networks results in low passive loss and small die size. Simple circuit techniques based on stability criteria derived result in an unconditionally stable amplifier. The power amplifier achieves a power gain of 7 dB and a maximum single-ended output power of +14.5-dBm with a 3-dB bandwidth of 3.1 GHz, while drawing 100 mA from a 2.8-V supply. The chip area is 1.26 mm/sup 2/.     

Bandwidth enhancement for transimpedance amplifiers

A technique for bandwidth enhancement of a given amplifier is presented. Adding several interstage passive matching networks enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known low-pass filter component values, is introduced. To demonstrate the feasibility of the method, a CMOS transimpedance amplifier (TIA) is implemented in a 0.18-/spl mu/m BiCMOS technology. It achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5-pF photodiode capacitance. This corresponds to a bandwidth enhancement ratio of 2.4 over the amplifier without the additional passive networks. The transresistance gain is 54 dB/spl Omega/, while drawing 55 mA from a 2.5-V supply. The input sensitivity of the TIA is -18 dBm for a bit error rate of 10/sup -12/.     

4H-SiC power bipolar junction transistor with a very low specific ON-resistance of 2.9 m/spl Omega//spl middot/cm/sup 2/

This letter reports a newly achieved best result on the specific ON-resistance (R/sub SP/spl I.bar/ON/) of power 4H-SiC bipolar junction transistors (BJTs). A 4H-SiC BJT based on a 12-/spl mu/m drift layer shows a record-low specific-ON resistance of only 2.9 m/spl Omega//spl middot/cm/sup 2/, with an open-base collector-to-emitter blocking voltage (V/sub ceo/) of 757 V, and a current gain of 18.8. The active area of this 4H-SiC BJT is 0.61 mm/sup 2/, and it has a fully interdigitated design. This high-performance 4H-SiC BJT conducts up to 5.24 A at a forward voltage drop of V/sub CE/=2.5 V, corresponding to a low R/sub SP-ON/ of 2.9 m/spl Omega//spl middot/cm/sup 2/ up to J/sub c/=859 A/cm/sup 2/. This is the lowest specific ON-resistance ever reported for high-power 4H-SiC BJTs.     

Design and analysis of novel high-gain and broad-band GaAs pHEMT MMIC distributed amplifiers with traveling-wave gain stages

Using the concept of traveling-wave gain stages, novel GaAs pseudomorphic high electron-mobility transistor monolithic-microwave integrated-circuit (MMIC) distributed amplifiers (DAs) are demonstrated to achieve high gain and over several octaves of bandwidth performance simultaneously for microwave and millimeter-wave frequency applications. The cascaded single-stage distributed amplifier (CSSDA) is used as traveling-wave gain stages to improve the gain performance of the conventional distributed amplifier (CDA). By adopting the low-pass filter topology between the CDA and CSSDA and tuning the gain shape of CDA and CSSDA separately, a broad-band and high-gain DA, called CDA-CSSDA-2, was accomplished. The detailed design equations are derived for the broad-band matching design of this CDA-CSSDA-2. Two other MMICs, namely, a two-stage CSSDA called 2-CSSDA, and another two-stage design called CDA-CSSDA-1, are also included in this paper. This CDA-CSSDA-2 achieves 22/spl plusmn/1.5-dB small-signal gain from 0.1 to 40 GHz with a chip size of 1.5/spl times/2 mm/sup 2/. It also produces a gain-bandwidth product of 503 GHz, which is the highest among all reported GaAs-based DAs. The flat group delay also demonstrates the feasibility of this design for future digital optical communications and broad-band pulse applications.     

A 32-GHz non-uniform distributed amplifier in 0.18-/spl mu/m CMOS

This letter presents a fully integrated distributed amplifier in a standard 0.18-/spl mu/m CMOS technology. By employing a nonuniform architecture for the synthetic transmission lines, the proposed distributed amplifier exhibits enhanced performance in terms of gain and bandwidth. Drawing a dc current of 45mA from a 2.2-V supply voltage, the fabricated circuit exhibits 9.5-dB pass-band gain with a bandwidth of 32GHz while maintaining good input and output return losses over the entire frequency band. With a compact layout technique, the chip size of the distributed amplifier including the testing pads is 940/spl times/860/spl mu/m/sup 2/.     

A 10 Gbit/s OEIC photoreceiver using InP/InGaAs heterojunction bipolar transistors

Metal organic molecular beam epitaxy (MOMBE) was successfully used for the first time to realise a high speed monolithic photoreceiver. Incorporating an InGaAs pin photodetector followed by a transimpedance preamplifier circuit implemented with InP/InGaAs heterojunction bipolar transistors (HBTs), the OEIC photoreceiver had a bandwidth of 6 GHz and a midband transimpedance of 350 Omega . In a system experiment performed at 10 Gbit/s, the receiver exhibited a sensitivity of -15.5 dBm for a bit error rate of 10/sup -9/ at a wavelength of 1.53 mu m. This is the first demonstration of operation of a long wavelength OEIC photoreceiver at this speed.<>     

SiGe differential transimpedance amplifier with 50-GHz bandwidth

InP and SiGe technologies are both attractive for design of circuits operating at 40 GB/s and beyond. In this paper, we describe a fully differential SiGe transimpedance amplifier (TIA) suitable for differential phase-shift keying applications. The TIA exhibits 49 dB-/spl Omega/ transimpedance, greater than 50-GHz bandwidth, and input-referred current noise less than 30 pA//spl radic/Hz. For comparison, we have also developed a similar TIA in an InP double-heterostructure bipolar transistor technology. The InP TIA had 48 dB-/spl Omega/ transimpedance and 49-GHz bandwidth.     

1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.     

An InGaAs-InP HBT differential transimpedance amplifier with 47-GHz bandwidth

Return-to-zero differential phase-shift keying applications require a differential amplifier with high bandwidth, high gain, low noise, and good input impedance match. In this paper, we describe an InGaAs-InP heterostructure bipolar transistor differential transimpedance amplifier with high bandwidth of 47 GHz and high gain of 56 dB-/spl Omega/. The input-referred current noise is less than 35 pA//spl radic/Hz over the measurement range up to 40 GHz.     

Development of screen-printed silicon solar cells with high fill factors on 100 /spl Omega//sq emitters

High-quality DuPont screen-printed Ag contacts were achieved on high sheet-resistance emitters (100 /spl Omega//sq) by rapid alloying of PV168 Ag paste. Excellent specific contact resistance (/spl sim/1 m/spl Omega/-cm/sup 2/) in conjunction with high fill factor (FF) (0.775) were obtained on 100 /spl Omega//sq emitters by a 900/spl deg/C spike firing of the PV168 paste in a belt furnace. The combination of the alloying characteristics of the PV168 Ag paste and optimized single-step rapid low-thermal budget firing resulted in a cost-effective manufacturable process for high-efficiency Si solar cells. In addition, the co-fired 100 /spl Omega//sq cell showed a noticeable improvement of /spl sim/0.5% in absolute efficiency over a conventional co-fired 45 /spl Omega//sq emitter cell. Lighter doping in the 100 /spl Omega//sq emitter cell resulted in better blue-response compared to the conventional cell, contributing to /spl sim/1.3 mA/cm/sup 2/ improvement in short-circuit current. Improved surface passivation on 100 /spl Omega//sq emitter cell resulted in additional 0.6 mA/cm/sup 2/ increase in J/sub sc/, 15-mV higher V/sub oc/, and a 0.6% increase in absolute cell efficiency. Front grid design optimization resulted in a FF of 0.780, and a further improvement in cell efficiency to reach 17.4%.     

Design, fabrication, and characterization of low forward drop, low leakage, 1-kV 4H-SiC JBS rectifiers

The 1-kV 4H-SiC planar junction barrier Schottky (JBS) rectifiers were designed, fabricated, and characterized. Different p+ implantation dosages and activation anneal methods were used to determine an optimum baseline process. Using the optimized process, the forward drop of our JBS rectifiers is <1.5 V while the reverse leakage current density is <1/spl times/10/sup -5/ A/cm/sup -2/. Blocking voltage>1 kV was achieved using a single-zone junction termination extension termination. It was shown experimentally that 4-/spl mu/m p-type implantation window spacing gives an optimum tradeoff between forward drop voltage and leakage current density for these rectifiers, yielding a specific on-resistance of 3 m/spl Omega//spl middot/cm/sup 2/.     

Monolithically integrated long wavelength photoreceiver OEIC based on InP/InGaAs HBT technology

The epitaxial structure and growth, circuit design, fabrication process and characterization are described for the photoreceiver opto-electronic integrated circuit (OEIC) based on the InP/lnGaAs HBT/PIN photodetector integration scheme. A 1.55 μm wavelength monolithically integrated photoreceiver OEIC is demonstrated with self-aligned InP/lnGaAs heterojunction bipolar transistor (HBT) process. The InP/lnGaAs HBT with a 2 μm × 8 μm emitter showed a DC gain of 40, a DC gain cutoff frequency of 45 GHz and a maximum frequency of oscillation of 54 GHz. The integrated InGaAs photodetector exhibited a responsivity of 0.45 AAV at λ = 1.55 μm, a dark current less than 10 nA at a bias of -5 V and a -3 dB bandwidth of 10.6 GHz. Clear and opening eye diagrams were obtained for an NRZ 223-l pseudorandom code at both 2.5 and 3.0 Gbit/s. The sensitivity for a bit error ratio of 10-9 at 2.5 Gbit/s is less than -15.2 dBm.     

A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-/spl mu/m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V//spl mu/s average slew rate while only dissipating 330 /spl mu/W at 1.5 V, when driving a 25-k/spl Omega///120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.     

4 kV 4H-SiC epitaxial emitter bipolar junction transistors

In this paper, we present 4H-SiC bipolar junction transistors (BJTs) with open-base blocking voltage (BV/sub CEO/) of 4000 V, specific on-resistance (R/sub on,sp/) of 56 m/spl Omega/-cm/sup 2/, and common-emitter current gain /spl beta//spl sim/9. These devices are designed with interdigitated base and emitter fingers with multiple emitter stripes. We assess the impact of design (emitter stripe width and contact spacing) on device performance and also examine the effect of emitter contact resistance on the device forward conduction characteristics.     

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs have been investigated. The doping concentration (dose) of the RESURF and lightly doped drain regions has been optimized to reduce the electric field crowding at the drain edge or in the gate oxide by using device simulation. The optimum oxidation condition depends on the polytype: N/sub 2/O oxidation at 1300/spl deg/C seems to be suitable for 4H-SiC, and dry O/sub 2/ oxidation at 1250/spl deg/C for 6H-SiC. The average inversion-channel mobility is 22, 78, and 68 cm/sup 2//Vs for 4H-SiC(0001), (112~0), and 6H-SiC(0001) MOSFETs, respectively. RESURF MOSFETs have been fabricated on 10-/spl mu/m-thick p-type 4H-SiC(0001), (112~0), and 6H-SiC(0001) epilayers with an acceptor concentration of 1/spl times/10/sup 16/ cm/sup -3/. A 6H-SiC(0001) RESURF MOSFET with a 3-/spl mu/m channel length exhibits a high breakdown voltage of 1620 V and an on-resistance of 234 m/spl Omega//spl middot/cm/sup 2/. A 4H-SiC(112~0) RESURF MOSFET shows the characteristics of 1230 V-138 m/spl Omega//spl middot/cm/sup 2/.     

Optical receiver IC for CD/DVD/blue-laser application

In this paper, an optoelectronic receiver IC for CD, DVD, and Blue-Laser optical data storage applications is presented. The IC was developed in a 0.5-/spl mu/m BiCMOS technology with integrated PIN photodiodes. It includes a new architecture of high-speed and low-noise variable gain transimpedance amplifiers witch current preamplifier input. The amplifier transimpedance gain is programmable over a gain range of 130 /spl Omega/ to 270 k/spl Omega/ by a serial interface. The amplifier small-signal bandwidth is 260 MHz for the highest gain, which gives a gain-bandwidth product of 70 THz/spl Omega/ and a sensitivity improvement by a factor of 2 compared to published OEICs. The amplifiers support a special write/clip mode which realizes a nonlinear gain reduction for high input signals. The output voltage buffers are 130-/spl Omega/ impedance matched for optimized data transmission over a flex cable. The impedance is generated by active-impedance synthesis to increase the output dynamic range.     

Design of broad-band lumped-element baluns with inherent impedance transformation

This paper reports on a novel lumped balun topology, the second-order lattice balun, with broad-band performance. The design is based on synthetic transmission lines operating as impedance transformers. The characteristic impedance of the synthetic transmission lines may be chosen to obtain inherent impedance transformation. An analytical investigation results in closed formulas for optimum performance over a given bandwidth. It is shown that it is possible to design for equal ripple in amplitude balance and input reflection coefficient. The phase balance is theoretically perfect over the entire bandwidth. The concept is experimentally validated by a 1-GHz prototype fabricated with surface mounted chip components. It exhibits an amplitude balance better than 0.5 dB and a phase balance better than /spl plusmn/8/spl deg/ over an octave bandwidth. The effective area of the prototype is 7 /spl times/ 9 mm/sup 2/.