High-frequency InP/InGaAs double heterojunction bipolar transistorson Si substrate

Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I_C=15 mA, f _T was 59 GHz at V_CE=1.8 V, and f _max was 69 GHz at V_CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V_CE of 3.8 V was applied for I_C=7.5 mA in the S-parameter measurements to give an f_T of 39 GHz and an f_max of 52 GHz     

The new two-dimensional electron gas base HBT (2DEG-HBT):two-dimensional numerical simulation

The bipolar/FET characteristics of the 2DEG-HBT are analyzed extensively by a two-dimensional numerical simulator based on a drift-diffusion model. For bipolar operations at high collector current densities, it is confirmed that the cutoff frequency f_T is determined mainly by the collector transit time of holes and by the charging time of the extrinsic base-collector capacitance C _bc^EXT. The charging times of the emitter and base regions and the base transit time are shown to be negligible. A high cutoff frequency F_T (88 GHz) and current gain h_FE (760) are obtained for an emitter size of 1×10 μm², and undoped collector thickness of 150 nm, and a collector current density J_c of 10⁵ A/cm². The FET operation of the same 2DEG-HBT structure shows a threshold voltage V_th of 0.74 V, the transconductance G_m^max of 80 mS/mm, and maximum cutoff frequency F_T^max of 15 GHz. The dependence of the device performance on material parameters is analyzed extensively from a device design point of view     

A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V_ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency (f_T) of 14 GHz with a collector-emitter breakdown voltage (BV_CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f_T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process     

CW measurement of HBT thermal resistance

Measurements of the temperature dependence of β and V_BE were made on AlGaAs-GaAs HBTs and used to determine device thermal resistance. The measurements were CW and not switched or pulsed in order to have a simpler procedure. With base doping greater than 10¹⁹ cm^-3, HBTs have negligible base-width modulation (i.e., flat I_C versus V_CE characteristics) which makes CW thermal resistance measurement especially direct and simple     

1/f noise in MODFETs at low drain bias

The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S_I/I² versus the effective gate voltage V_G=V_GS-V_off shows three regions which are explained. The observed dependencies are S_I/I²∝V_G ^m with the exponents m=-1, -3, 0 with increasing values of V_G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m=0 at large V_G or V_GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V_G , m=-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance     

Experimental values for the hole diffusion coefficient andcollector transit velocity in P-n-p AlGaAs/GaAs HBTs

The diffusion coefficient (D_h) and a value for the collector velocity (v_h) of holes in AlGaAs/GaAs P-n-p HBTs (heterojunction bipolar transistors) were obtained from high-frequency measurements on structures with different base and collector widths. Quantities for D_h and v _h of 5.6 cm²/s and 5.5×10⁶ cm/s, respectively, were obtained by plotting the total emitter-collector delay versus inverse emitter current and extrapolating the data to infinite emitter current to obtain the base and collector transit delays. An f_t and f_max as high as 15 and 29 GHz, respectively, were obtained for non-self-aligned (1-μm emitter mesa/base contact separation) devices with a 2.6-μm×10-μm emitter     

High-speed performance of Si/Si1-xGexheterojunction bipolar transistors

A theoretical investigation of Si/Si_1-xGe_x heterojunction bipolar transistors (HBTs) undertaken in an attempt to determine their speed potential is discussed. The analysis is based on a compact transistor model, and devices with self-aligned geometry, including both extrinsic and intrinsic parameters, are considered. For an emitter area of 1×5 μm², an f_t of over 75 GHz and f_max of over 35 GHz were computed at a collector current density of 1×10 ⁵ A/cm² and V_CB of 5 V     

The effect of substrate bias on hot-carrier damage in NMOS devices

Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V_d =8 V and V_g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V_b), having a power-law gradient of 0.5 for V_b=0 V and 0.3 for V_b=-9 V. Investigation of the type of damage resulting from stressing shows that at V_b=0 V, interface state generation results, while at V_b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions     

Collector-assisted operation of micromachined field-emitter triodes

The field at the tip of a field emitter triode can be expressed by E=βV_g+_γV _c, where V_g and V_c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, _γV_c<<βV _g. The-device is operated in the gate-induced field emission mode and the corresponding I-V_c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I-V_c and transconductance g_m-V_g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly     

Measurement of collector and emitter resistances in bipolartransistors

New DC methods to measure the collector resistance R_C and emitter resistance R_E are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R_C. R_E is obtained from the measured lateral portion of R_C and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R_C on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R_C is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R_E a value for the specific contact resistance for the polysilicon emitter contact of ρ_c≅50 Ω-μm² is obtained     

Co-integration of resonant tunneling and double heterojunctionbipolar transistors on InP

The authors report the first co-integration of resonant tunneling and heterojunction bipolar transistors. Both transistors are produced from a single epitaxial growth by metalorganic molecular beam epitaxy, on InP substrates. The fabrication process yields 9-μm²-emitter resonant tunneling bipolar transistors (RTBTs) operating at room temperature with peak-to-valley current ratios (PVRs) in the common-emitter transistor configuration, exceeding 70, at a resonant peak current density of 10 kA/cm², and a differential current gain at resonance of 19. The breakdown voltage of the In_0.53Ga_0.47As-InP base/collector junction, V_CBO, is 4.2 V, which is sufficient for logic function demonstrations. Co-integrated 9-μm²-emitter double heterojunction bipolar transistors (DHBTs) with low collector/emitter offset voltage, 200 mV, and DC current gain as high as 32 are also obtained. On-wafer S-parameter measurements of the current gain cutoff frequency (f_T) and the maximum frequency of oscillation (f_max) yielded f _T and f_max values of 11 and 21 GHz for the RTBT and 59 and 43 GHz for the HBT, respectively     

A coupled study by floating-gate and charge-pumping techniques ofhot carrier-induced defects in submicrometer LDD n-MOSFET's

The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V_d/8 to V_d) by hot-hole and/or hot-electron injections, and their generation rates (10^-9 and 10^-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I_d-V_g degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I _d-V_g degradation     

Electron transport in 0.15-μm gate In0.52Al0.48As/In0.53Ga0.47As HEMT

Magneto-transport and cyclotron resonance measurements were made to determine directly the density, mobility, and the effective mass of the charge carriers in a high-performance 0.15-μm gate In_0.52 Al_0.48As/In_0.53Ga_0.47As high-electron-mobility transistor (HEMT) at low temperatures. At the gate voltage V_G=0 V, the carrier density n _g under the gate is 9×10¹¹ cm^-2, while outside of the gate region n_g=2.1×10¹² cm^-2. The mobility under the gate at 4.2 K is as low as 400 cm²/V-s when V_G<0.1 V and rapidly approaches 11000 cm²/V-s when V_G>0.1 V. The existence of this high mobility threshold is crucial to the operation of the device and sets its high-performance region in V_G>0.1 V     

Si/a-Si:H heterojunction microwave bipolar transistors with cut-offfrequencies ft above 5 GHz

The fabrication of a silicon heterojunction microwave bipolar transistor with an n⁺ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V_CE=6 V, I_c=15 mA), and an emitter Gummel number G _E of about 1.4×10¹⁴ Scm^-4. From the measured S parameters, a cutoff frequency f_t of 5.5 GHz and maximum oscillating frequency f_max of 7.5 GHz at V_CE=10 V, I_c=10 mA are obtained     

A multiple-state memory cell based on the resonant tunneling diode

The device consists primarily of several molecular-beam-epitaxy (MBE-) grown GaAs/(AlGa)As resonant tunneling diodes connected in parallel. This device exhibits multiple peaks in the I-V characteristic. When a load resistor is connected, the circuit can be operated in a multiple stable mode. With this concept, implementation of three-state and four-state memory cells are made. In the three-state case the operating points at voltages V₀=0.27 V , V₁=0.42 V, and V₂=0.53 V represent the logic levels 0, 1, and 2. Similarly for the four-state memory cell the logic levels voltages are V₀=0.35 V, V₁=0.42 V, V₂=0.54 V, and V ₃=0.59 V. A suggestion of an integrated device structure using this concept is also presented     

High/fmax collector-up AlGaAs/GaAsheterojunction bipolar transistors with a heavily carbon-doped basefabricated using oxygen-ion implantation

AlGaAs/GaAs collector-up heterojunction bipolar transistors (HBTs) with a heavily carbon-doped base layer were fabricated using oxygen-ion implantation and zinc diffusion. The high resistivity of the oxygen-ion-implanted AlGaAs layer in the external emitter region effectively suppressed electron injection from the emitter, allowing collector current densities to reach values above 10⁵ A/cm ². For a transistor with a 2-μm×10-μm collector, f_T was 70 GHz and f_max was as high as 128 GHz. It was demonstrated by on-wafer measurements that the first power performance of collector-up HBTs resulted in a maximum power-added efficiency of as high as 63.4% at 3 GHz     

Application of the floating-gate technique to the study of then-MOSFET gate current evolution due to hot-carrier aging

The evolution of the gate current-voltage (I_g- V_gs) characteristics of n-MOSFETs induced by DC stresses at different gate voltage over drain voltage (V_ds ) ratios is studied by the floating-gate (FG) measurement technique. It is shown that the I_g-V_gs curves are always lowered after aging, and that the kinetics are dependent on the aging conditions. A time power law is representative of the V_gs=V_ds case. It is demonstrated that electron traps are created in the oxide by both hot-hole and hot-electron injection stresses. They are not present in the devices before aging. They can be easily charged and discharged by short electron and hole injections, respectively     

The electron impact ionization rate and breakdown voltage inGaAs/Ga0.7Al0.3As MQW structures

The electron impact ionization rate (α) and breakdown voltage (V_BD) experimentally measured in a p⁺ -i-n⁺ diode structure with a GaAs/Ga_0.7Al _0.3As multiple quantum-well (MQW) i region are discussed. For structures with GaAs wells of 100 Å and barriers that vary from 7 to 60 Å in thickness, it is found that α is always less than α in bulk GaAs and that it decreases with increasing barrier thickness. The normalized V_BD also increases with increasing barrier thickness, confirming a decreasing ionization rate     

Self-aligned SiGe-base heterojunction bipolar transistor byselective epitaxy emitter window (SEEW) technology

In the device a SiGe epitaxial base is integrated in a structure which uses in situ doped epitaxial lateral overgrowth for the formation of the emitter window and the extrinsic base contact. Nearly ideal I -V characteristics have been achieved for a base width of 60 nm with an intrinsic base resistance of 4.6 kΩ/□ and for emitter widths down to 0.4 μm. A DC collector current enhancement factor of 3.1 was obtained relative to a Si homojunction transistor with a 1.25 times higher intrinsic base resistance. The breakdown voltage BV_CBO is identical for both Si and SiGe devices, even though the collector-base depletion region is partly overlapped with the reduced-bandgap SiGe strained layer. The lower BV_CEO, measured for the SiGe-base transistor, is due to the higher current gain. Based on these results the fabrication of high-speed bipolar circuits that take advantage of SiGe-base bandgap engineering seems possible using selective epitaxy emitter window (SEEW) technology     

A new two-mode channel FET (TMT) for super-low-noise and high-powerapplications

A super-low-noise two-mode channel FET (TMT) with high- and plateau-shaped transconductance (g_m) characteristics has been developed. It has two electron transport modes against the applied gate voltage (V_gs). That is, the electrons mainly drift in a highly doped channel region at a shallow V_gs. A plateau g_m region and the maximum g_m were achieved at a V_gs range of -0.25~+0.5 V and 535 mS/mm, respectively. The minimum noise figure and associated gain for the TMT were superior in the low-drain-current (I_ds) region and nearly equal in the middle and high I_ds region to those of an AlGaAs/InGaAs pseudomorphic HEMT fabricated using the same wafer process and device geometry