基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

p沟道锗/硅异质纳米结构MOSFET存储器及其逻辑阵列

采用巴丁(Bardeen)传输哈密顿方法,数值计算了p沟道锗/硅异质纳米结构存储器的时间特性.由于台阶状隧穿势垒和较高价带带边的作用,这种新型的存储器单元可以同时实现器件的快速编程和长久存储,具有优异的存储特性.以2×2逻辑阵列为例说明了这类存储器单元组成逻辑电路的设计原理.研究结果表明:这种器件可以作为在室温下工作的性能优异的非易失性存储器单元,有望在将来的超大规模集成电路中获得应用.     

p沟道锗/硅异质纳米结构MOSFET存储器及其逻辑阵列

采用巴丁(Bardeen)传输哈密顿方法,数值计算了p沟道锗/硅异质纳米结构存储器的时间特性.由于台阶状隧穿势垒和较高价带带边的作用,这种新型的存储器单元可以同时实现器件的快速编程和长久存储,具有优异的存储特性.以2×2逻辑阵列为例说明了这类存储器单元组成逻辑电路的设计原理.研究结果表明:这种器件可以作为在室温下工作的性能优异的非易失性存储器单元,有望在将来的超大规模集成电路中获得应用.     

复合量子点MOSFET结构存储器的电路模拟

本文采用准经典近似的Monte Carlo方法对复合量子点MOSFET结构存储器的等效单电子电路进行了模拟.研究结果表明,由于台阶状的复合隧穿势垒的作用,存储器的存储时间特性可得到极大提高.我们进一步研究了N沟道锗/硅复合量子点MOSFET结构存储器的时间特性,得到其存储时间可长达数年,同时写擦时间可分别为μs和ns量级,从而这种新型的器件结构可以有效解决快速编程和长久存储间的矛盾.     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

Ge/Si复合纳米结构电荷存储特性的模拟研究

这一研究工作模拟计算了 Ge/ Si复合纳米结构 MOSFET存储器的擦写和存储时间特性。结果表明 ,Ge/ Si复合纳米结构存储器在低压下即可实现 μs和 ns量级编程。与 Si纳米结构存储器相比 ,由于 Ge/ Si复合势阱的作用 ,器件的电荷保留时间提高了 3～ 5个量级 ,有效地解决了快速擦写编程与长久存储之间的矛盾 ,使器件的性能得到明显改善。     

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

基于硅纳米晶的非挥发存储器制备与存储特性

硅纳米晶非挥发存储器由于其卓越的性能以及与传统工艺的高度兼容性,近来引起高度关注。采用两步低压化学气相淀积(LPCVD)生长方式制备硅纳米晶(Si-NC),该方法所制备的硅纳米晶具有密度高、可控性好的特点,且完全兼容于传统CMOS工艺。在此基础上制作四端硅纳米晶非挥发存储器,该器件展示出良好的存储特性,包括10 V操作电压下快速地擦写,数据保持特性的显著提高,以及在105次擦写周期以后阈值电压(Vt)飘移低于10%的良好耐受性。该器件在未来高性能非挥发存储器应用上极具潜质。     

电子空穴对单电子陷阱存储器的设计与分析

本文论述了由Ti/TiOx/Ti介观隧道结阵列构成的电子空穴对耦合的单电子陷阱存储器,结合目前扫描隧道显微镜(STM)进行纳米加工的特点,设计了该存储器的电路结构及其结构参数,计算出电路的电容矩阵,并用Monte Carlo法对电路特性进行了模拟.结果表明,该存储器与其它单电子存储器有相同的存储特性,但具有较高的工作温度及工作稳定性.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

Comparison of III–V Heterostructures Grown on Ge/Si,Ge/SOI,and GaAs

Semiconductors - III–V/Ge/Si(001), III–V/Ge/SOI(001), and III–V/GaAs(001) heterostructures are fabricated and investigated. The Ge buffer layer for the III–V/Ge/Si structure...     

GaAs Shallow-homojunction solar cells on Ge-coated Si substrates

Solar cells with conversion efficiencies of 12% (AM1) have been fabricated from single-crystal GaAs epilayers grown by CVD on Ge-coated Si substrates. The cells utilize an n⁺/p/p⁺shallow-homo junction GaAs structure on a thin (<0.2 µm) epitaxial Ge layer. These solar cells are the first reported GaAs devices fabricated on Si substrates.     

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.     

Si基Ge波导光电探测器的制备和特性研究

以外延Ge薄膜为吸收区,在Si基上制备了Ge波导光电探测器。利用超高真空化学汽相淀积(UHV/CVD)设备,采取低温高温两步法,在Si(100)衬底上外延出厚度约为500nm的高质量纯Ge层。探测器采用脊型波导结构,Al电极分别制作在波导的台面上下形成背对背肖特基结。I-V特性测试表明,在-1V偏压下,暗电流密度为0.2mA/cm2。由于Si与Ge热失配引起外延的Ge薄膜受到0.2%张应变,减小了Ge带隙,光响应波长范围扩展到1.60μm以上。在70mW、1.55μm入射光照射下,测得光电流比暗电流高出近1个数量级。     

Electron mobility enhancement in strained-Si n-MOSFETs fabricatedon SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si_1-xGe_x-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si_0.75Ge_0.26 and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si_1-xGe_x layer     

Si/GexSi1-x heterojunction bipolartransistors with the GexSi1-x base formed by Geion implantation in Si

We have fabricated n-p-n, Si/Ge₂Si_1-x heterojunction bipolar transistors (HBTs) with the Ge_xSi_1-x base formed by high-dose Ge implantation followed by solid phase epitaxy. The fabrication technology is a standard self-aligned, double polysilicon process scheme for Si with the addition of the high-dose Ge implantation. The transistors are characterized by a 60 mn-wide neutral base with a Ge concentration peak of ≈8 at.% at the base-collector junction. The HBTs show good electrical characteristics and compared to Si homojunction transistors show lower base resistance, larger values of current gain, and a lower emitter-to-collector transit time     

Application of silicon-germanium in the fabrication of ultra-shallow extension junctions for sub-100 nm PMOSFETs

This work summarizes the results of several experiments to investigate the potential applications of Silicon-Germanium alloy in the fabrication of shallow source/drain (S/D) extension Junctions for deep submicron PMOS transistors. Two approaches were used for the fabrication of p/sup +/-Si/sub 1-x/Ge/sub x//n-Si heterojunctions. In the first approach, high dose Ge ion implantation followed by boron implantation into Si was used to form very shallow p/sup +/-Si/sub 1-x/Ge/sub x//n-Si junctions (x/spl les/0.2). In the second approach, thin Ge films were deposited onto Si substrates by conventional low pressure chemical vapor deposition. This was followed by boron implantation into the Ge and thermal annealing to co-diffuse Ge and B atoms into Si and form p/sup +//n heterojunctions. The electrical characteristics of the heterojunction diodes were comparable to those of conventional Si (homo) junctions. Secondary ion mass spectrometry (SIMS) concentration-depth profiles indicate that dopant segregation in the Si/sub 1-x/Ge/sub x/ regions resulted in the formation of ultra-shallow and abrupt junctions that could be used as S/D extensions for sub-100 nm CMOS generations. PMOS transistors fabricated using these techniques exhibit superior short-channel performance compared to control devices, for physical gate lengths down to 60 nm.     

p-type Ge-channel MODFETs with high transconductance grown on Sisubstrates

Modulation-doped FET (MODFET) structures with hole channels consisting of pure Ge were grown by molecular beam epitaxy (MBE) on Si substrates. To overcome the relatively large lattice mismatch, between Si and Ge, a relaxed Si_1-xGe_x buffer layer with linearly graded Ge concentration and a final x value of around 70% was grown first. Hall mobilities of up to 1300 cm²/V-s at room temperature and 14000 cm²/V-s at 77 K were measured. Devices with and without gate recess were fabricated, which result in enhancement- and depletion-type FETs. Maximum extrinsic transconductances of 125 and 290 mS/mm at room temperature and 77 K, respectively, were found for gate lengths L_G around 1.2 μm     

Band-gap narrowing and high-frequency characteristics ofSi/GexSi1-x heterojunction bipolar transistorsformed by Ge ion implantation in Si

Si/Ge_xSi_1-x heterojunction n-p-n bipolar transistors (HBT's) with a double-polysilicon self-aligned structure were fabricated by using high dose Ge implantation for the formation of the Si/Ge_xSi_1-x heterostructure and As and BF₂ implantation for emitter and base doping. DC and high frequency electrical characteristics are investigated for Ge concentrations up to 7 at.% and for base widths down to 35 nm. Improvements in electrical characteristics compared to reference Si transistors are demonstrated. Experimental data indicating that these improvements are related to an effective band gap engineering are shown and discussed