基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

基于硅纳米晶的非挥发存储器制备与存储特性

硅纳米晶非挥发存储器由于其卓越的性能以及与传统工艺的高度兼容性,近来引起高度关注。采用两步低压化学气相淀积(LPCVD)生长方式制备硅纳米晶(Si-NC),该方法所制备的硅纳米晶具有密度高、可控性好的特点,且完全兼容于传统CMOS工艺。在此基础上制作四端硅纳米晶非挥发存储器,该器件展示出良好的存储特性,包括10 V操作电压下快速地擦写,数据保持特性的显著提高,以及在105次擦写周期以后阈值电压(Vt)飘移低于10%的良好耐受性。该器件在未来高性能非挥发存储器应用上极具潜质。     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

纳米晶非挥发性存储器研究进展

介绍了纳米晶非挥发性存储器的发展状况和基本工作原理,比较了纳米晶非挥发性存储器所涉及到的各种不同的电荷输运机制,系统介绍了纳米晶非挥发性存储器在纳米晶材料设计、纳米晶晶体生长控制方法、隧穿/控制介质层工程和新型存储器器件结构等方面的一些最新研究进展,对纳米晶非挥发性存储器的研究趋势进行了展望。     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

纳米晶存储特性的研究

常温下硅纳米晶构成的MOSFET存储器具有低压、低功耗、体积小、高剂量和快速读写等优良特性,在ULSI中有重要的应用前景.它是当前ULSI研究中的一项热门专题,在国外一些著名刊物上屡见报道.本文介绍了这种器件的存储特性及其机理与最新研究进展.     

硅纳米晶存储器的耐受性研究

首先介绍了硅纳米晶粒的制备工艺以及硅纳米晶存储器件的基本特性。接着重点探讨了硅纳米晶存储器耐久性退化的物理机制,发现应力引起的界面陷阱是耐受性退化的主要原因。随后,同时采用多种分析手段,如电荷泵法和CV曲线分析法对界面陷阱的退化机理进行了更深入细致的研究。从界面陷阱在禁带中的能级分布中发现,相较于未施加应力时界面陷阱的双峰分布,施加应力后产生了新的Pb1中心的双峰。最后,分别从降低擦写电压和对载流子预热的角度提出了三种新的编程方法,有效提高了硅纳米晶存储器件的耐受性。     

p沟道锗/硅异质纳米结构MOSFET存储器及其逻辑阵列

采用巴丁(Bardeen)传输哈密顿方法,数值计算了p沟道锗/硅异质纳米结构存储器的时间特性.由于台阶状隧穿势垒和较高价带带边的作用,这种新型的存储器单元可以同时实现器件的快速编程和长久存储,具有优异的存储特性.以2×2逻辑阵列为例说明了这类存储器单元组成逻辑电路的设计原理.研究结果表明:这种器件可以作为在室温下工作的性能优异的非易失性存储器单元,有望在将来的超大规模集成电路中获得应用.     

p沟道锗/硅异质纳米结构MOSFET存储器及其逻辑阵列

采用巴丁(Bardeen)传输哈密顿方法,数值计算了p沟道锗/硅异质纳米结构存储器的时间特性.由于台阶状隧穿势垒和较高价带带边的作用,这种新型的存储器单元可以同时实现器件的快速编程和长久存储,具有优异的存储特性.以2×2逻辑阵列为例说明了这类存储器单元组成逻辑电路的设计原理.研究结果表明:这种器件可以作为在室温下工作的性能优异的非易失性存储器单元,有望在将来的超大规模集成电路中获得应用.     

Ni纳米晶制备及其在MOS电容中存储特性研究

优化了Ni纳米晶的制备工艺参数,得到了分布均匀,形状为球形,平均尺寸5nm,密度2×1012/cm2的Ni纳米晶。在此基础上,制备了包含Ni纳米晶的MOS电容结构。利用高频电容-电压(C-V)和电导-电压(G-V)测试研究了其电学性能,证明该MOS电容结构的存储效应主要源于金属纳米晶的限制态。电容-时间(C-t)测试曲线呈指数衰减趋势,保留时间600s,具有较好的保留性能。     

Ge/Si复合纳米结构电荷存储特性的模拟研究

这一研究工作模拟计算了 Ge/ Si复合纳米结构 MOSFET存储器的擦写和存储时间特性。结果表明 ,Ge/ Si复合纳米结构存储器在低压下即可实现 μs和 ns量级编程。与 Si纳米结构存储器相比 ,由于 Ge/ Si复合势阱的作用 ,器件的电荷保留时间提高了 3～ 5个量级 ,有效地解决了快速擦写编程与长久存储之间的矛盾 ,使器件的性能得到明显改善。     

Nonvolatile Charge Injection Memory Based on Black Phosphorous 2D Nanosheets for Charge Trapping and Active Channel Layers

2D van der Waals atomic crystal materials have great potential for use in future nanoscale electronic and optoelectronic applications owing to their unique properties such as a tunable energy band gap according to their thickness or number of layers. Recently, black phosphorous (BP) has attracted significant interest because it is a single‐component material like graphene and has high mobility, a direct band gap, and exhibits ambipolar transition behavior. This study reports on a charge injection memory field‐effect transistor on a glass substrate, where few‐layer BPs act as the active channel and charge trapping layers, and Al₂O₃ films grown by atomic layer deposition act as the tunneling and blocking layers. Because of the ambipolar properties of BP nanosheets, both electrons and holes are involved in the charge trapping process, resulting in bilateral threshold voltage shifts with a large memory window of 22 V. Finally, a memory circuit of a resistive‐load inverter is implemented that converts analog signals (current) to digital signals (voltage). Such a memory inverter also shows a clear memory window and distinct memory on/off switching characteristics.     

Room‐Temperature Nonvolatile Memory Based on a Single‐Phase Multiferroic Hexaferrite

The cross‐coupling between electric polarization and magnetization in multiferroic materials provides a great potential for creating next‐generation memory devices. Current studies on magnetoelectric (ME) applications mainly focus on ferromagnetic/ferroelectric heterostructures because single‐phase multiferroics with strong magnetoelectric coupling at room temperature are still very rare. Here a type of nonvolatile memory device is presented solely based on a single‐phase multiferroic hexaferrite Sr₃Co₂Fe₂₄O₄₁ which exhibits nonlinear magnetoelectric effects at room temperature. The principle is to store binary information by employing the states (magnitude and sign) of the first‐order and the second‐order magnetoelectric coefficients (α and β), instead of using magnetization, electric polarization, and resistance. The experiments demonstrate repeatable nonvolatile switch of α and β by applying pulsed electric fields at room temperature, respectively. Such kind of memory device using single‐phase multiferroics paves a pathway toward practical applications of spin‐driven multiferroics.     

Low‐Power Nonvolatile Charge Storage Memory Based on MoS2 and an Ultrathin Polymer Tunneling Dielectric

Low‐power, nonvolatile memory is an essential electronic component to store and process the unprecedented data flood arising from the oncoming Internet of Things era. Molybdenum disulfide (MoS₂) is a 2D material that is increasingly regarded as a promising semiconductor material in electronic device applications because of its unique physical characteristics. However, dielectric formation of an ultrathin low‐k tunneling on the dangling bond‐free surface of MoS₂ is a challenging task. Here, MoS₂‐based low‐power nonvolatile charge storage memory devices are reported with a poly(1,3,5‐trimethyl‐1,3,5‐trivinyl cyclotrisiloxane) (pV3D3) tunneling dielectric layer formed via a solvent‐free initiated chemical vapor deposition (iCVD) process. The surface‐growing polymerization and low‐temperature nature of the iCVD process enable the conformal growing of low‐k (≈2.2) pV3D3 insulating films on MoS₂. The fabricated memory devices exhibit a tunable memory window with high on/off ratio (≈10⁶), excellent retention times of 10⁵ s with an extrapolated time of possibly years, and an excellent cycling endurance of more than 10³ cycles, which are much higher than those reported previously for MoS₂‐based memory devices. By leveraging the inherent flexibility of both MoS₂ and polymer dielectric films, this research presents an important milestone in the development of low‐power flexible nonvolatile memory devices.     

硅纳米晶粒基MOSFET存储器的荷电特征研究

本文研究了硅纳米晶粒MOSFET存储器的荷电特征.器件阈值电压偏移达1.8V以上,并随着沟道宽度的变窄而增加,而与沟道长度基本无关.同时,阈值涨落也随宽度的变窄而增大.在20~300K测量温度范围内,器件阈值偏移和电荷的存储特性几乎不随温度变化,说明荷电过程主要由直接隧穿决定.进一步,在最窄沟道器件中观察到单电荷的荷电过程.     

Nonvolatile Ferroelectric P(VDF‐TrFE) Memory Transistors Based on Inkjet‐Printed Organic Semiconductor

Nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) memory based on an organic thin‐film transistor with inkjet‐printed dodecyl‐substituted thienylenevinylene‐thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of ?12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 cm²/Vs, 10⁵, and 10^?10 A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.     

Flexible Nonvolatile Transistor Memory Devices Based on One‐Dimensional Electrospun P3HT:Au Hybrid Nanofibers

A novel flexible nonvolatile flash transistor memory devices on polyethylene naphthalate (PEN) substrate using 1D electrospun nanofiber of poly(3‐hexylthiophene) (P3HT):gold nanoparticles (Au NPs) hybrid as the channel is presented. The Au NPs are functionalized with self‐assembled monolayer (SAM) of para‐substituted amino (Au‐NH₂), methyl (Au‐CH₃) or trifluoromethyl (Au‐CF₃) tail groups on the benzenethiol moiety. They are employed as localized charge traps across the nanofiber channel and program/erase the device towards low conductance (OFF)/high conductance (ON) states under the applied electrical field. With the low operation voltage of ±5 V, the hybrid nanofiber transistor memories exhibit a 3.5–10.6 V threshold voltage shifting and at least 10⁴ s data retention, with a minimum effect on ≈100 programmed/erased stress endurances. The dipoles of the SAM probably modify the work function of the Au NPs associated with the P3HT nanofiber channel and manifest the degree of negative threshold voltage shifting in an order of Au‐NH₂ > Au‐CH₃ > Au‐CF₃. The devices remain reliable and stable even under the bending conditions (radius: 5–30 mm) or 1000 repetitive bending cycles. The hybrid nanofiber can be used to obtain high‐performance digital nanoscale memories for flexible high density data storage devices.