A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

This study proposes a 300‐mA external capacitor‐free low‐dropout (LDO) regulator for system‐on‐chip and embedded applications. To achieve a full‐load range from 0 to 300 mA, a two‐scheme (a light‐load case and a heavy‐load case) operation LDO regulator with a novel control circuit is proposed. In the light‐load case (0–0.5 mA), only one P‐type metal–oxide–semiconductor input‐pair amplifier with a 10‐pF on‐chip capacitor is used to obtain a load current as low as 0. In the heavy‐load case (0.5 to 300 mA), both P‐type metal–oxide–semiconductor and N‐type metal–oxide–semiconductor differential input‐pair amplifiers with an assistant push‐pull stage are utilized to improve the stability of the LDO regulator and achieve a high slew rate and fast‐transient response. Measurements show an output voltage of 3.3 V and a full output load range from 0 to 300 mA. A line regulation of 1.66 mV/V and a load regulation of 0.0334 mV/mA are achieved. The measured power‐supply rejection ratio at 1 kHz is −65 dB, and the measured output noise is only 34 μV. The total active chip size is approximately 0.4 mm² with a standard 0.5 μm complementary metal–oxide–semiconductor process. Copyright © 2017 John Wiley & Sons, Ltd.     

Pathological representation of the two‐output CCII and ICCII family and application

The pathological mirror and nullor representation of the two‐output current conveyor family is given. New pathological mirror and nullor representations of the two‐output current conveyor family are given and compared with the corresponding nullator norator resistors' realizations. Simplified representations of the two‐output current conveyors based on using two single‐output current conveyors are given. Two examples are given, the first example demonstrates the importance of the pathological representation in the generation of a family of 16 oscillators from a two‐output current conveyor‐based current mode oscillator. A second example of a current mode low‐pass filter using two single‐output inverting current conveyors is considered. Its simplified modeling using a single balanced output inverting current conveyor is compared with the original current mode filter and the simulation results are given. Copyright © 2010 John Wiley & Sons, Ltd.     

Selectivity and sensitivity enhancement methods for high‐data‐rate super‐regenerative receiver

This paper describes selectivity and sensitivity performance evaluations and improvement methods for an on–off keying super‐regenerative (SR) receiver. A slope‐controlled quasi‐exponential quench waveform, generated by a low‐complexity PVT‐tolerant quench generator circuit, is proposed to increase data rate and reduce the receiver 3‐dB bandwidth, thereby preventing oscillation caused by out‐of‐band injected signals and improving the receiver selectivity. The SR receiver sensitivity is also enhanced by a noise‐canceling front‐end topology with single‐ended to differential (S2D) signal converter. To exemplify these techniques, we designed an SR receiver with the proposed front‐end and quench waveform generator in a 0.18‐μm CMOS technology. Theoretical analyses and circuit simulations show 30% and 65% reduction in 3‐dB bandwidth of the SR receiver at 25 Mbps data rate by employing the proposed quench signal compared with piecewise‐linear and trapezoidal quench waveforms, respectively. Performance of the proposed front‐end is evaluated by a fast bit‐error‐rate estimation procedure, based on circuit noise simulations and statistical analyses, without the need for time‐consuming transient‐noise simulations. Accuracy of the procedure has been verified by comparing its results with transient‐noise simulations. According to the estimated bit‐error‐rate curves, the noise‐canceling topology with S2D converter enhances the SR receiver sensitivity by 9 dB. Copyright © 2017 John Wiley & Sons, Ltd.     

Graphical analysis and design of multistage operational amplifiers with active feedback Miller compensation

Frequency compensation of a multistage operational amplifier (op‐amp) is normally performed through solving nodal equations of an equivalent circuit to obtain the op‐amp's final transfer function. The process is often very tedious and offers little insight into the roles of the selected compensation scheme. In this paper, we present a graphical design approach for two‐stage and three‐stage op‐amps with active feedback Miller compensation. By viewing frequency compensation as a standard feedback problem, we can utilize the well‐known graphical tools such as the root locus and Bode plot to understand the effects of the compensation and to estimate the locations of the closed‐loop poles and zeros of the op‐amp. Intuitive graphical design procedures for two‐stage and three‐stage op‐amps are also formulated. To show its effectiveness, we illustrate our design approach through the design of a three‐stage op‐amp in a standard 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS) process. With a load capacitance of 500 pF, post‐layout simulations show that the op‐amp achieves a low‐frequency gain of 144 dB, a phase margin of 58^°, and a unity‐gain frequency of 1.38 MHz while consuming a total bias current of 31 μA from a 1.8‐V supply voltage. Comparisons with the published amplifiers show that our op‐amp achieves the figure of merits comparable to those of the state of the art. Copyright © 2015 John Wiley & Sons, Ltd.     

Hyperchaos and horseshoe in a 4D memristive system with a line of equilibria and its implementation

We study a four‐dimensional system modified from a three‐dimensional chaotic circuit by adding a memristor, which is a new fundamental electronic element with promising applications. Although the system has a line of infinitely many equilibria, our studies show that when the strength of the memristor increases, it can exhibit rich interesting dynamics, such as hyperchaos, long period‐1 orbits, transient hyperchaos, as well as non‐attractive behaviors frequently interrupting hyperchaos. To verify the existence of hyperchaos and reveal its mechanism, a horseshoe with two‐directional expansion is studied rigorously in detail by the virtue of the topological horseshoe theory and the computer‐assisted approach of a Poincaré map. At last, the system is implemented with an electronic circuit for experimental verification. Copyright © 2013 John Wiley & Sons, Ltd.     

Analysis and realization of a switched fractional‐order‐capacitor integrator

Using fractional calculus, we analyze a classical switched‐capacitor integrator when a fractional‐order capacitor is employed in the feed‐forward path. We show that using of a fractional‐order capacitor, significantly large time constants can be realized with capacitances in the feedback path much smaller in value when compared with a conventional switched‐capacitor integrator. Simulations and experimental results using a commercial super‐capacitor with fractional‐order characteristics confirmed via impedance spectroscopy are provided. Copyright © 2016 John Wiley & Sons, Ltd.     

Design and simulation of novel amplifier‐based mixer for ISM band wireless applications

This letter describes a low‐voltage low‐power (LV‐LP) 2.4‐GHz mixer for Industrial, Scientific and Medical (ISM) band wireless applications. The approach is based on a two‐stage amplifier, and the Gilbert switch stage is inserted between the two amplifier stages. The proposed amplifier‐based mixer delivers a remarkable conversion gain of 13 dB with a local oscillator (LO) power of 7 dBm, while consuming only 1.05‐mW DC power from a 0.8‐V supply voltage. The input‐referred third‐order intercept point (IIP3) of the mixer is 3.82 dBm, and the chip area is only 0.429 mm². The results indicate that this mixer is suitable for the low‐voltage low‐power applications. Copyright © 2014 John Wiley & Sons, Ltd.     

Structure generation and performance comparison of elliptic Gm‐C filters

Starting from a set of matrices describing a general G_m‐C filter topology, a procedure is developed for generating structures of lowpass filters. As the matrices and the filter topologies have a one‐to‐one correspondence, an algebraic method is used to identify filter topologies with desired properties, here, transfer functions with finite jω‐axis transmission zeros, specifically elliptic filters. Sensitivity expressions for these structures are derived and a performance comparison based on a set of chosen criteria is made. For a specified elliptic transfer function, filters with only grounded capacitors and those containing also floating capacitors emerge as alternative realizations, as are filters with a single input and those with distributed inputs. For third‐order functions, a detailed comparison is performed of leapfrog (LF) and inverse follow‐the‐leader‐feedback (IFLF), the most popular special cases, and of topologies that have also floating capacitors (LF_f, IFLF_f), as well as of a novel configuration that uses also distributed inputs (DI_f) and leads to a reduced element count. Design guidelines and restrictions are given, which follow from the derived results with focus on the circuits' sensitivity performance and other properties important for IC implementation. Copyright © 2004 John Wiley & Sons, Ltd.     

Design and analysis of a millimeter‐wave injection locked frequency divider with transconductance boosting technique

This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I‐V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter‐wave injection‐locked frequency dividers. To compensate the degradation of mixer transconductance (conversion‐gain) due to the degeneration effect, a neutralization technique is employed. Analyses are given for locking‐range and induced phase‐noise of the proposed divider for arbitrary injection strength. It is shown that the locking‐range, as a function of injection strength, is improved by increasing the fundamental component of transconductance. Using 180‐nm CMOS technology, a 1.78‐mW divider‐by‐two is designed with free‐running frequency of 27.92 GHz, locking‐range of 51 to 59.6 GHz, and figure‐of‐merit of 4.83 (GHz/mW). EM simulation results of the proposed and conventional structure are compared, which illustrates 56% improvement in locking‐range.     

Analytical synthesis and comparison of voltage‐mode Nth‐order OTA‐C universal filter structures

Complementary single‐ended‐input operational transconductance amplifier (OTA)‐based filter structures are introduced in this paper. Through two analytical synthesis methods and two transformations, one of which is to convert a differential‐input OTA to two complementary single‐ended‐input OTAs, and the other to convert a single‐ended‐input OTA and grounded capacitor‐based one to a fully differential OTA‐based one, four distinct kinds of voltage‐mode nth‐order OTA‐C universal filter structures are proposed. TSMC H‐Spice simulations with 0.35µm process validate that the new complementary single‐ended‐input OTA‐based one holds the superiority in output precision, dynamic and linear ranges than other kinds of filter structures. Moreover, the new voltage‐mode band‐pass, band‐reject and all‐pass (except the fully differential one) biquad structures, all enjoy very low sensitivities. Both direct sixth‐order universal filter structures and their equivalent three biquad stage ones are also simulated and validated that the former is not absolutely larger in sensitivity than the latter. Finally, a very sharp increment of the transconductance of an OTA is discovered as the operating frequency is very high and leads to a modified frequency‐dependent transconductance. Copyright © 2010 John Wiley & Sons, Ltd.     

Evaluation of energy saving and CO2 emission reduction technologies in energy supply and end‐use sectors using a global energy model

Assessments of global warming mitigation technologies are important for achieving the Kyoto target and planning post‐Kyoto regimes. Regional differences in energy resources, growth in energy consumption, current technology diffusions, etc., should be considered in the assessments. A global energy systems model, DNE21+, with high regional resolution had treated the energy supply sectors in a bottom‐up fashion and the end‐use sectors in a top‐down fashion, which was expressed by using long‐term price elasticity. However, the assessments of technological options in the end‐use sectors are currently more important, particularly for the near and middle terms. In order to evaluate the technological options not only in the energy supply sectors but also in the end‐use sectors for energy savings and CO₂ emission reductions, DNE21+ has been modified for treating two energy‐intensive end‐use sectors, i.e. steel and cement sectors, in the bottom‐up fashion. The results reveal that the cost‐effective global CO₂ emission reductions in 2030 for stabilizing the atmospheric CO₂ concentration at 550 ppmv in comparison with that in the reference case would be approximately 68 MtC/yr and almost zero in the steel and cement sectors, respectively. The cost‐effective options include next‐generation coke ovens and coke dry quenching (CDQ) in the steel sector. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

A linearized and low noise CMOS mixer with B‐type amplifier‐based sub‐harmonic balun

A low noise and high linearity down‐conversion CMOS mixer for 2.4‐GHz wireless receiver is presented in this paper. Using a sub‐harmonic balun with a simple but effective B‐type amplifier, the local oscillator frequency required for this mixer has been reduced by half, and the input local oscillator signal could be single‐ended rather than differential, which simultaneously simplifies the design of local oscillator. A distortion and noise cancelation transconductor in association with current bleeding technique is employed to improve the noise and linearity of the entire mixer under a reduced bias current without compromising the voltage gain. Fabricated in a 0.18‐µm RF CMOS technology of Global Foundries, the mixer demonstrates a voltage gain of 15.8 dB and input‐referred third‐order intercept point of 6.6 dBm with a noise figure of 2.6 dB. It consumes 7.65 mA from a 1.0‐V supply and occupies a compact area of 0.75 × 0.71 mm² including all test pads. Copyright © 2016 John Wiley & Sons, Ltd.     

The theory of instantaneous power in three‐phase four‐wire systems and its applications

This paper discusses “the p–q theory” and “the cross‐vector theory” in three‐phase four‐wire systems, with the focus on similarities and differences between the two theories. They are perfectly identical if no zero‐sequence voltage is included in a three‐phase three‐wire system. However, they are different in definition of the instantaneous active power and instantaneous reactive power in each phase if a zero‐sequence voltage or current is included in a three‐phase four‐wire system. Based on both theory and computer simulation, this paper leads to the following conclusions: An instantaneous reactive‐power compensator without energy storage components can fully compensate for the neutral current even in a three‐phase four‐wire system including a zero‐sequence voltage or current, when a proposed control strategy based on the p–q theory is applied: However, the compensator cannot compensate for the neutral current fully, when a conventional control strategy based on the cross‐vector theory is applied. © 2001 Scripta Technica, Electr Eng Jpn, 135(3): 74–86, 2001     

A single‐stage LED streetlight driver with PFC and digital PWM dimming capability

This paper proposes a single‐stage light‐emitting diode (LED) driver that offers power‐factor correction and digital pulse–width modulation (PWM) dimming capability for streetlight applications. The presented LED streetlight driver integrates an alternating current–direct current (AC–DC) converter with coupled inductors and a half‐bridge‐type LLC DC–DC resonant converter into a single‐stage circuit topology. The sub‐circuit of the AC–DC converter with coupled inductors is designed to be operated in discontinuous‐conduction mode for achieving input‐current shaping. Zero‐voltage switching of two active power switches and zero‐current switching of two output‐rectifier diodes in the presented LED driver decrease the switching losses; thus, the circuit efficiency is increased. A prototype driver for powering a 144‐W‐rated LED streetlight module with input utility‐line voltages ranging from 100 to 120 V is implemented and tested. The proposed streetlight driver features cost‐effectiveness, high circuit efficiency, high power factor, low levels of input‐current harmonics, and a digital PWM dimming capability ranging from 20% to 100% output rated LED power, which is fulfilled by a micro‐controller. Satisfying experimental results, including dimming tests, verify the feasibility of the proposed LED streetlight driver. Copyright © 2016 John Wiley & Sons, Ltd.     

Analysis and design of a dual‐mode control flyback converter

This letter presents a dual‐mode control scheme to improve the efficiency of a flyback converter in a wide load range. The proposed flyback converter features a novel dual‐mode operation. The valley‐switching technique is adopted to reduce the switching loss at light load. On the other hand, the fixed off‐time (FOT) controls with continuous conduction mode operations decrease the conduction losses at heavy load. The principles and design procedures of the proposed dual‐mode controller are discussed and analyzed. Finally, a 140‐W dual‐mode flyback converter with an output voltage of 19 V is implemented. Experimental results agree with the theoretical analysis. Copyright © 2012 John Wiley & Sons, Ltd.     

Temperature‐dependent modeling and performance analysis of coupled MLGNR interconnects

The temperature‐dependent circuit modeling and performance in terms of propagation delay, power dissipation, and crosstalk‐induced voltage waveform at the far end of victim line of multilayer graphene nanoribbon (MLGNR) interconnects have been analyzed at 22 nm technology node. A comparative performance analysis between MLGNR interconnects with resistance estimated using temperature‐dependent model and temperature‐independent model is examined. The results obtained are also compared with capacitively coupled interconnects of copper (Cu). The results show that as the temperature is varied from 300 K to 500 K, MLGNR has lower propagation delay and power dissipation as compared to Cu for 1 mm long interconnects. It is also observed that because of the dominance of both low resistance and ground capacitance compared to Cu, MLGNR has better crosstalk‐induced delay and voltage waveforms with rise in temperature at the far end of aggressor and victim line, respectively. Further, simulated results show an average relative improvement in propagation delay of 37.24% and corresponding improvement in power dissipation of approximately 19.59% by using a temperature‐dependent model in comparison to a temperature‐independent model of MLGNR resistance with interconnect lengths varying from 200 to 1000 μm. The reduction in the time duration of victim output pulse over these interconnect lengths also shows a significant improvement of approximately 35% by using temperature‐dependent model as against temperature‐independent model of MLGNR resistance.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

M‐matrices and global convergence of discontinuous neural networks

The paper considers a general class of neural networks possessing discontinuous neuron activations and neuron interconnection matrices belonging to the class of M‐matrices or H‐matrices. A number of results are established on global exponential convergence of the state and output solutions towards a unique equilibrium point. Moreover, by exploiting the presence of sliding modes, conditions are given under which convergence in finite time is guaranteed. In all cases, the exponential convergence rate, or the finite convergence time, can be quantitatively estimated on the basis of the parameters defining the neural network. As a by‐product, it is proved that the considered neural networks, although they are described by a system of differential equations with discontinuous right‐hand side, enjoy the property of uniqueness of the solution starting at a given initial condition. The results are proved by a generalized Lyapunov‐like approach and by using tools from the theory of differential equations with discontinuous right‐hand side. At the core of the approach is a basic lemma, which holds under the assumption of M‐matrices or H‐matrices, and enables to study the limiting behaviour of a suitably defined distance between any pair of solutions to the neural network. Copyright © 2006 John Wiley & Sons, Ltd.     

A high‐resolution hybrid digital pulse width modulator with dual‐edge‐triggered flip‐flops and hardware compensation

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) which applies a counter, a phase‐shifted circuit, and a carry chain is proposed. Dual‐edge‐triggered flip‐flops are used in the phase‐shifted circuit to generate signals with 45° phase shift, which not only improves the resolution of the DPWM but also reduces the resource consumption in the carry chain. Furthermore, a hardware compensation method is used to solve the duty cycle increment phenomenon that affects the regulation accuracy of converter. An 11‐bit DPWM with the proposed architecture is implemented and tested by Xilinx Artix‐7 FPGA. The experimental results show a high resolution of 32 ps and a good linearity where R² is 0.99 and verify the effect of duty cycle compensation.