单一单位增益放大器的Q增强SC滤波器

本文阐述了采用单位增益放大器的SC滤波器的设计方法。基于无源Q增强技术,由Sallew Key有源RC电路导出了一系列Q增强的二阶SC低通、高通和带通滤波器。设计表明,本文提出的Q增强SC电路比文献给出的电路需要小得多的电容分散度。本文考察了这些电路灵敏度和有限GB对SC电路的影响。用分立元件做了实验,实验结果与理论计算相吻合。     

RC oscillators with oscillation frequency independent of the op.-amp. gain-bandwidth product

Applying the determining equation proposed by Chua and Tang (1982), a frequency sensitivity problem in RC op.-amp. based oscillators is considered. A new expression for the sensitivity of oscillation frequency, ω_o, to changes in any oscillator parameter is developed. Then, the condition for this frequency to be insensitive to changes in the gain-bandwidth products (GB) of the op.-amp. used in the oscillator is formulated. Examples of two circuits exhibiting a zero sensitivity of ω_o to the GB changes (a very desirable feature) are presented. The first example represents oscillators with a single op.-amp. whose slew-rate effect is the only oscillator non-linearity. The second example concerns oscillators with a so-called composite amplifier where non-linear elements included in the oscillator feedback network are responsible for amplitude stabilization.     

多功能开关电流双二次滤波器生成

本文提出了一个具有差分输出的通用开关电流一阶积木块，并阐述了采用该积木块生成多功能ＳＩ滤波器的系统方法，以单放大器，两放大器和三放大器有源ＲＣ或ＳＣ网络为原型，系统地导出了一系列新的ＳＩ双二次结构，生成的所有ＳＩ电路均可在单一积木块上同时获得低通、高通和带通滤波功能，这些电路的灵敏度低，且为纯ＭＯＣ管结构，非常适合于数字ＣＭＯＳ工艺集成。     

一种新的开关电流双二次滤波器

本文阐述了开关电流(SI)和开关电容(SC)电路的相似性原理,由此提出了一个新的SI双二次滤波器电路,该电路是由文献[5]的三运放SC双二次电路为原型导出的。该电路的一个重要特征是:它在单一积木块上能同时获得低通、带通和高通滤波功能。据此,得到了SI电路的一般双二次实现。     

Compact formulation for exact analysis of nonideal SC circuits

A systematic analysis procedure to obtain closed-form expressions for the z-domain transfer functions of SC circuits with finite GB product op-amps is presented. This method allows exact frequential analysis of a general class of SC circuits, without imposing any restriction in the ratio between GB and clock frequencies.     

减小电容分布的单放大器开关电容带通滤波器

本文将正反馈引入到单放大器无限增益负反馈结构中,提出了四个新的带有部分正反馈的单放大器开关电容带通滤波器,得到了这些电路在给定极点频率ω_0和(?)值的设计方程和最小电容分布的最佳设计。同文献中的电路相比,本文电路的电容分布得到大幅度地减小。     

CMOS differential current conveyors and applications for analog VLSI

Novel differential current conveyor building blocks are defined. CMOS realizations of these blocks are then given. One of the proposed conveyor circuits is seen to be insensitive to the threshold voltage variation due to the body effect. The properties of the differential current conveyors are shown to be suitable for VLSI applications employing MOS transistors operating in the ohmic region. This is demonstrated by realizing four quadrant multiplier cells, current mode and mixed mode continuous time MOSFET-C filters based on the proposed blocks. PSPICE simulations indicate the excellent performance of the differential current converyor circuits.     

一个开关电容电路的模拟和优化程序

本文介绍了一个以分析开关电容(SC)电路为目的面向用户的通用程序。该程序可以完成对SC电路的时域、频域和灵敏度模拟,可以对SC电路进行多目标优化,并可以求得SC电路的传输极点,且对电路的输入信号、开关序列、网络拓扑没有限制,文中提出了在改进节点法基础上求出电路传输极点的方法,以贡献的方式建立求传输函数对电容比的灵敏度方程,通过线性变换求得对电容比的灵敏度的方法和SC电路的多目标优化方法。最后给出了用该程序对SC电路进行模拟和优化的两个算例。     

Electronically tunable grounded immittance simulators using an EX-CCCII

ABSTRACT

In this paper, electronically tunable grounded immittance simulators are presented. Each of the proposed circuits employs a single Extra X Current Controlled Current Conveyers (EX-CCCII) and a single grounded capacitor. First, two circuits provide lossless positive grounded inductance. These circuits offer different lossless/lossy immittance circuits with some changes in the connection at the Z-terminals of EX-CCCII. The circuits do not require any constraint for component matching and exhibit low parasitic effects. The circuits can be tuned electronically by varying the bias current of EX-CCCII. As application examples, some of the proposed circuits are used to realise a tunable second-order band-pass filter and a tunable high pass filter. The functionality of the proposed immittance simulators is verified through PSPICE simulation using 0.25µm TSMC CMOS technology parameters. The experimental results are also included using commercially available IC’s AD-844.     

Transient analysis of charge-transfer in SC filters-gain error and distortion

In switched-capacitor (SC) circuits, op amps often slew during the charge-transfer transient. When this happens, the charge-transfer error is no longer proportional to the input signal. The charge-transfer transient is studied in detail, taking into account the slewing behavior of the amplifiers. Analytical expressions are obtained for the charge-transfer error of an SC integrator. In switched-capacitor signal processing, the harmonic distortion can be defined as the harmonic distortion of the envelope of the sampled-data sequence. A Fourier analysis is carried out on the sampled-data sequence corrupted by the charge-transfer error due to slewing of the operational transconductance amplifiers. Analytical expressions are derived for harmonic distortions of an SC integrator. Analysis of the results shows that slew-induced harmonic distortion can be minimized by using large transconductance. It is possible to design SC filters with low power consumption and low harmonic distortion without resorting to class AB amplifiers.     

Switched-capacitor interpolators without the input sample-and-holdfiltering effect

The authors propose new switched-capacitor (SC) interpolators whose frequency responses are no longer affected by the input sample-and-hold filtering effect which occurred in previous circuits. Two different types of architectures are discussed, one for input sampled-and-hold signals, and the other for arbitrary input signal formats. Examples are given to illustrate both types of SC interpolator circuits     

Pseudo-N-path switched capacitor filters with out-of-band noise peaks

Novel pseudo-N-path (PNP) switched-capacitor (SC) integrator structures which avoid noise peaks in the main passband are described. They combine the simplicity of the previously proposed RAM-type PNP SC circuits with the desirable properties of hybrid-type circuits. Simulation results are presented for filters employing these structures to verify their usefulness.<>     

Realization of Series and Parallel R-L and C-D Impedances Using Single Differential Voltage Current Conveyor

In this paper, realization of series and parallel R-L immitances using differential voltage current conveyor (DVCC) is presented. The proposed circuits enable actively simulation series and parallel R-L and (-R)-(-L) immitances. Applying RC:CR transformation to the proposed configurations, series and parallel C-D and (-C)-(-D) simulators can also be realized with the same topology. They employ single DVCC and at most three resistors and one capacitor. No component matching constraints are imposed for the realisations. The performance of the proposed immittance simulators is demonstrated on both a second-order voltage and second-order current-mode filters. PSPICE simulations are given to verify the theoretical analysis. An erratum to this article is available at .     

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.     

基于信号流图的开关电流滤波器设计

开关电流（SI）是有望取代开关电容（SC）的一种新型的取样数据技术，鉴于SC技术发展的成熟性及其与SI技术的紧密联系，即SC和SI滤波电路具有互易性，可采用信号流图转置的方法，将SC综合法直接用于SI滤波器设计，而无须提出新的设计方法。本文以二阶巴特沃思开关电容带通滤皮器为例给出了该方法的具体应用。     

Low-voltage dynamic biasing technique for CMOS class ABcurrent-mode circuits

A novel dynamic biasing technique that can be used for the design of CMOS class AB current-mode circuits is presented. The approach takes advantage of the switched capacitor (SC) technique and enables extremely low voltage operations. An application of the proposed technique to the design of a basic input stage is given and simulations showing good agreement with the expected results are provided     

RFI-induced distortion in switched-capacitor circuits

The errors which are induced by radio-frequency interference (RFI) in switched-capacitor (SC) circuits are discussed and the main role played by the distortion of MOS switches in the on-state is highlighted. Furthermore, a new simple analytical model, which enables one to predict RFI-induced errors in SC circuits is proposed and it is validated by the comparison of its predictions with time-domain computer simulation results.     

Built-In-Self-Testing Techniques for Programmable Capacitor Arrays

This paper presents efficient built-in-self-testing (BIST) techniques for programmable capacitor arrays (PCAs) on field programmable analog array (FPAA) platforms. The proposed BIST circuits consist of switched-capacitor (SC) integrators and analog window comparators. Taking advantage of FPAA programmable resources, the proposed PCA BIST circuits can be implemented with very small hardware overhead. Also the impact of comparator threshold variations as well as other circuit parasitic effects on the efficiency of the proposed testing method is investigated. Effective circuit techniques along with new comparator designs are presented to minimize the adverse effect of comparator threshold variations. Finally, procedures for using the proposed BIST method to systematically test all PCAs on an FPAA platform are described and experimental results are presented.     

A precision low-power analog front end in 180 nm CMOS for wireless implantable capacitive pressure sensors

This paper presents a new capacitance to voltage analog-front end (AFE) designed in 180 nm CMOS technology for wireless implantable applications. This AFE consists of a Low-dropout regulator (LDO), bandgap reference (BGR), switched-capacitor (SC) sampler, SC op-amp and oscillator. The LDO regulates the wireless power supply coming from an off-chip rectifier and provides a stable and accurate DC voltage. Capacitance is converted to a discrete voltage by a SC sampling circuit and then amplified by a SC op-amp. Both of SC sampling and SC op amp circuits form a correlated double sampling scheme. This AFE is designed to sense a capacitance range from 6 pF to 7 pF (300–1000 mmHg) corresponding to a 0.68 V–1.07 V discrete output voltage with a sampling frequency of 1.63 KHz. This AFE has a sensitivity of 0.39 mV/fF, average power consumption of 201 μW and 3.25% accuracy operating over a 2.1 V–3.3 V rectified wireless supply voltage and −40 °C ~125 °C temperature range.     

SC amplifier and SC integrator with an accurate gain of 2

A fully differential switched-capacitor (SC) amplifier and integrator with an accurate gain of 2 are proposed. Both circuits are based on a novel capacitor mismatch compensation scheme which uses the same capacitor as the charge sampling and summing element. Therefore, the gain error which is linearly proportional to the capacitor mismatch in conventional SC circuits becomes proportional to the square of the mismatch. In addition, the proposed scheme does not require additional active blocks, and the valid output is generated within two clock cycles.