Reconfiguring fault-tolerant two-dimensional array architectures

Circuit complexities reduce overall reliability and mean-time-between-failure rates of today's very large processing arrays. Our integrated, three-level hierarchy of reconfiguration methods provides reasonable levels of fault tolerance for such systems. Operating in a completely distributed fashion, the hierarchy does not require that any components be fault free. It significantly improves array reliability by using a combination of transient fault rollback techniques and local and global reconfiguration algorithms     

Reconfiguring system hierarchies with multi-valued logic

We propose a mathematical formalism to define a system hierarchy and choose a way to reconfigure it based on multi-valued logic. We consider an application of this formalism to control over a group surveying the danger zone after a natural disaster.     

Reconfiguring wireless phones with adaptive chips

Cellular phone manufacturers are on the horns of a dilemma. On one hand, the demand for their products continues to grow. On the other hand, cellular-phone technology is also changing rapidly. Vendors are dealing with this problem by using an adaptive (also called reconfigurable) chips in a new way. With this approach, software can redraw a chip's physical circuitry on the fly, letting a single processor perform multiple functions. In addition, adaptive computing could increase performance while reducing energy consumption.     

Security in SRAM FPGAs

As FPGAs have grown larger and more complex, the value of the IP implemented in them has grown commensurately. Since SRAM FPGAs reload their programming data every time they are powered up, an adversary can potentially copy the program as it is being loaded. FPGA manufacturers have added security features to protect designs from unauthorized copy, theft, and reverse-engineering as the bitstream is transmitted from permanent storage into the FPGA. These bitstream security features use well-known information security methods to protect design data. In this discussion, it is assumed that an adversary has physical access to the FPGA. In this environment, denial-of-service attacks on the configuration are irrelevant: A trivial denial-of-service method would be to physically damage the device - the so-called "whack-it-with-a-hammer" attack.     

Sorting networks on FPGAs

Computer architectures are quickly changing toward heterogeneous many-core systems. Such a trend opens up interesting opportunities but also raises immense challenges since the efficient use of heterogeneous many-core systems is not a trivial problem. Software-configurable microprocessors and FPGAs add further diversity but also increase complexity. In this paper, we explore the use of sorting networks on field-programmable gate arrays (FPGAs). FPGAs are very versatile in terms of how they can be used and can also be added as additional processing units in standard CPU sockets. Our results indicate that efficient usage of FPGAs involves non-trivial aspects such as having the right computation model (a sorting network in this case); a careful implementation that balances all the design constraints in an FPGA; and the proper integration strategy to link the FPGA to the rest of the system. Once these issues are properly addressed, our experiments show that FPGAs exhibit performance figures competitive with those of modern general-purpose CPUs while offering significant advantages in terms of power consumption and parallel stream evaluation.     

Energy-Efficient Computations on FPGAs

Recently, energy dissipation for computations on FPGAs has become an important performance metric. In this paper, we summarize our recent efforts in developing an algorithm-level design methodology for optimizing the energy performance of FPGA based implementations. For kernels, our design methodology consists of four steps: domain selection, domain-specific energy modeling, domain-space exploration and low-level simulation. To achieve system-level energy-efficiency, we outline a design methodology that integrates the kernel-level design methodology. Both the design methodologies can be used to achieve not only energy-efficiency but also latency, area, and power efficiency. We consider signal processing kernels as illustrative examples and demonstrate energy and time efficient algorithms and implementations for these on FPGAs. Example energy performance optimization through algorithmic optimizations include the 29–51% improvement in energy performance for a matrix multiplication kernel, 57–78% improvement for a FFT kernel and the 10–60% improvement for a floating-point LU decomposition kernel over state-of-the-art implementations. Similarly, an improvement of 41 to 46% in energy performance was achieved by the system-level design approach over a greedy approach for a MVDR adaptive beamforming application. Finally we briefly describe a high-level tool for obtaining parameterized and energy-efficient designs on FPGAs.This work is supported by the National Science Foundation under award No. CCR-0311823.     

Neural classifiers using one-time updating

The linear threshold element, or perceptron, is a linear classifier with limited capabilities due to the problems arising when the input pattern set is linearly nonseparable. Assuming that the patterns are presented in a sequential fashion, we derive a theory for the detection of linear nonseparability as soon as it appears in the pattern set. This theory is based on the precise determination of the solution region in the weight spare with the help of a special set of vectors. For this region, called the solution cone, we present a recursive computation procedure which allows immediate detection of nonseparability. The algorithm can be directly cast into a simple neural-network implementation. In this model the synaptic weights are committed. Finally, by combining many such neural models we develop a learning procedure capable of separating convex classes.     

A one-time signature using run-length encoding

A one-time signature scheme using run-length encoding is presented, that in the random oracle model offers security against chosen-message attacks. For parameters of interest, the proposed scheme enables about 33% faster verification with a comparable signature size than a construction of Merkle and Winternitz. The public key size remains unchanged (1 hash value). The main price for the faster verification is an increase of the time for signing messages and for key generation.     

Privacy-preserving e-payments using one-time payment details

The recent increase in data breaching incidents involving high profile e-commerce companies is alarming as such privacy threats can seriously thwart the healthy growth of electronic commerce. We propose a privacy-preserving e-payment scheme that guarantees authenticity while keeping the customer’s sensitive details secret from the respective parties involved in the online transaction. Using a non-reusable password-based authentication approach, the proposed protocol allows consumers to anonymously purchase goods from an online merchant, thus achieving the ideal privacy environment in which to shop. The protocol can be easily deployed in an e-commerce environment without requiring great changes to the current processes.     

基于收发器的全系列FPGA

带宽和数据速率的提高需要更多、更快的收发器。各种标准以及对优异的背板信号完整性和协议兼容性的需求推动了数字器件收发器技术的创新与发展。为满足不同市场和应用的需求,数字器件必须在密度和特性上达到最佳组合,同时满足性能、功耗和成本目标。本文介绍了如何利用Altera最全面的收发器定制逻辑系列产品和技术创新来满足这些需求。     

最先进的10万门现场可编程门阵列（FPGAs）

本文介绍了国际上最新的10万门FPGA系列，该产品由美国GateField公司研制，采用Flash存储器作为控制码存储单元以及一种和掩膜式门阵列类似的“细粒”可编程逻辑单元，其单元面积大大小于现在市场上的SRAM结构和EPROM结构的FPGA及EPLD单元，目前采用0．8μm工艺已达10万门高密度。本文对其多层次“瓦片”式结构也作了较详细介绍。     

一种高档FPGA可重构配置方法

在多模式导航接收机中,FPGA可重构技术能将硬件资源进行时分复用,从而大大降低系统的复杂性和成本.在对高档FPGA可重构技术深入研究的基础上,设计了用CPLD FLASH对FPGA进行重构配置的硬件电路,给出了对CPLD进行硬件描述的Verilog HDL程序,结果表明该方法是可行的.     

Reconfiguring Triangulations with Edge Flips and Point Moves

We examine reconfigurations between triangulations and near-triangulations of point sets. We give new bounds on the number of point moves and edge flips sufficient for any reconfiguration. We show that with O(n log n) edge flips and point moves, we can transform any geometric near-triangulation on n points to any other geometric near-triangulation on n possibly different points. This improves the previously known bound of O(n²) edge flips and point moves. We then show that with a slightly more general point move, we can further reduce the complexity to O(n) point moves and edge flips.     

Dynamic reconfiguration architectures for multi-context FPGAs

Field-programmable gate arrays (FPGAs) are being integrated with processors on the same motherboard or even chip in order to achieve flexible high-performance computing, and this may become main stream in chip multi-core architectures. However, the expensive FPGA area is often used inefficiently, with much of the logic idle at any given time. This work, motivated by the Dynamic-Link Library (DLL) concept in software, explores the possibility of “hardware DLLs” by finding ways for fast dynamic incremental reconfiguration of FPGAs. So doing would, among other things, enable same-function replication at any given time, with functions changing quickly over time, thereby enabling efficient exploitation of data parallelism at no additional hardware cost.We present two new multi-context FPGA architectures based on two different configuration storage architectures: local and centralized. Problems such as configuration storage and reconfiguration (time, power and space) overhead are considered. Well known area and power models are used in evaluating various approaches and in order to provide guidelines for matching architectures to target applications. Lastly, we provide insights into resulting scheduling issues. Our findings provide the foundation and “rules of the game” for subsequent development of reconfiguration schedulers and execution environments.     

Designing fault-tolerant techniques for SRAM-based FPGAs

FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuit's operation. We present a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CEO) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques.     

过程性纹理映射的FPGA动态生成

在FPGA可编程硬件平台上设计实现了基于珀林噪声函数的过程性纹理生成算法.该算法充分利用了FPGA硬件设计的优势,针对这一算法基于像素密集求解的特点,更快、更好地进行设计实现.利用该算法可以实时地生成许多不同的自然材质或现象的纹理,如木料、云石、云朵等,其纹理可以随时间动态变换,以产生真实的运动效果.文中采用了一种新的珀林（Perlin）噪声函数,以充分应用硬件电路的结构特点,耗费较少的硬件资源,达到各种运算单元（如加法和乘法）模块的组合和高度复用.     

Processors and FPGAs Quo Vadis?

Electronic applications continue to demand increased flexibility, configurability, and performance, along with reduced power consumption, board space, and cost. This is increasing pressure to integrate analog, memory, logic, and soft microcontroller unit (MCU) implementations into a single-system chip. As a result, analog, microcontroller, and application-specific integrated circuit (ASIC) suppliers are adding configurability to their product lines. As the race to develop programmable system chip solutions heats up, field-programmable gate array (FPGA) suppliers have a leg up on the competition because programmable logic has proved to be the most difficult of the necessary technologies to master     

Single pass streaming BLAST on FPGAs

Approximate string matching is fundamental to bioinformatics and has been the subject of numerous FPGA acceleration studies. We address issues with respect to FPGA implementations of both BLAST- and dynamic-programming- (DP) based methods. Our primary contribution is a new algorithm for emulating the seeding and extension phases of BLAST. This operates in a single pass through a database at streaming rate, and with no preprocessing other than loading the query string. Moreover, it emulates parameters turned to maximum possible sensitivity with no slowdown. While current DP-based methods also operate at streaming rate, generating results can be cumbersome. We address this with a new structure for data extraction. We present results from several implementations showing order of magnitude acceleration over serial reference code. A simple extension assures compatibility with NCBI BLAST.     

Altera新型FPGA器件的配置方式

介绍了如何对Altera的新型FPGA器件Cyclone系列进行配置，Cyclone支持使用被动配置（Ps）、主动配置（AS）、JTAG配置方式中的任何一种，或者是它们的组合配置方式。     

用现场可编程门阵列设计前向神经网络

本文给出了利用现场可编程门阵列来实现多层前向神经网络(反向传播-BP网络)的方法.首先利用了相关软件在理论上作了算法上的仿真,在此基础上构建了前向神经网络的硬件结构.主要使用了查找表的方式来实现Sigmoid激励函数,并给出了解决异或问题的硬件上的具体方案.最后给出了BP网络解决异或问题的Quartus Ⅱ仿真结果,表明了方案的可行性.