共查询到16条相似文献,搜索用时 62 毫秒
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一种高性能CMOS采样/保持电路 总被引:1,自引:0,他引:1
介绍了一种高性能CMOS采样/保持电路.该电路在3 V电源电压下,60 MHz采样频率时,输入直到奈奎斯特频率仍能够达到90 dB的最大信号谐波比(SFDR)和80 dB的信噪比(SNR).电路采用全差分结构、底板采样、开关栅电压自举(bootstrap)和高性能的增益自举运算放大器.采用0.18 μm CMOS工艺库,对电路进行了Hspice仿真验证.结果表明,整个电路消耗静态电流5.8 mA. 相似文献
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一种高速高精度采样/保持电路 总被引:1,自引:0,他引:1
介绍了一种用于12bit,100MS/s流水线模数转换器前端的采样/保持电路的设计.该电路在3V电源电压100MHz采样频率时,输入直到奈奎斯特频率仍能够达到108dB的无杂散动态范围(SFDR)和77dB的信躁比(SNR).论文建立了考虑开关之后的采样保持电路的分析模型,并详细研究了电路中开关组合对电路性能的影响,同时发现了传统的栅源自举开关(bootstrapped switch)中存在的漏电现象并对其进行了改进,极大地减小了漏电并提高了电路的线性性能. 相似文献
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AD781是Analog Devices公司生产的快速采样保持放大器,它具有采样时间短、下降速度慢、保持误差小、功耗低、功能齐备、体积小等优点,十分适用于高速AD转换器的前端电路。本文介绍了采样保持放大器AD781的性能参数及应用电路。 相似文献
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一种用于流水线A/D转换器的低功耗采样/保持电路 总被引:1,自引:0,他引:1
文章介绍了一种适用于10位20MS/s流水线A/D转换器的采样/保持(S/H)电路。该电路为开关电容结构,以0.6μm DPDM CMOS工艺实现。采用差分信号输入结构,降低对共模噪声的敏感度,共模反馈电路的设计稳定了共模输出,以达到高精度。该S/H电路采用低功耗运算跨导放大器(OTA),在5V电源电压下,功耗仅为5mW。基于该S/H电路的流水线A/D转换器在20MHz采样率下,信噪比(SNR)为58dB,功耗为49mW。 相似文献
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A newly designed sample-and-hold(S/H) integrated circuit based on the 1.5 micron N-well CMOS technology for 8-bit high-speed analog to digital converter is described. It can realize the 40-MHz sampling rate and 8-bit resolution. The good performance of S/H circuit benefits from the use of a newly designed regulated cascode operator amplifier, which has a DC gain of 140-dB, unity-gain bandwidth of 407-MHz, phase margin of 53 degree and power consumption of 90mW. It is superior to the operator amplifier of 60-dB, 107-MHz, 13 degree, and 33mW respectively, which is used in the similar S/H circuit based on the 0. 8 micron technology and designed by Michio Yotsuyanagi. 相似文献
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The sample-and-hold (S/ H) circuit is a key module for many applications[1 ] totransform a continuous time signal into discrete one. In analog to digital (A/ D)converters,the front-end of the S/ H amplifier must be of both high speed... 相似文献
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用于10位100 MS/s流水线A/D转换器的采样保持电路 总被引:2,自引:0,他引:2
设计了一个用于10位100 MHz采样频率的流水线A/D转换器的采样保持电路。选取了电容翻转结构;设计了全差分套筒式增益自举放大器,可以在不到5 ns内稳定在最终值的0.01%内;改进了栅压自举开关,减少了与输入信号相关的非线性失真,提高了线性度。采用TSMC 0.25μm CMOS工艺,2.5 V电源电压,对电路进行了仿真和性能验证,并给出仿真结果。所设计的采样保持电路满足100 MHz采样频率10位A/D转换器的性能要求。 相似文献
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Haruo Kobayashi Mohd Asmawi Mohamed Zin Kazuya Kobayashi Hao San Hiroyuki Sato Jun-Ichi Ichimura Yoshitaka Onaya Yuuichi Takahashi Naoki Kurosawa Yasuyuki Kimura Yasushi Yuminaka Kouji Tanaka Takao Myono Fuminori Abe 《Analog Integrated Circuits and Signal Processing》2001,27(1-2):165-176
This paper describes the design of a high-speed CMOSTrack/Hold circuit in front of an ADC. The Track/Hold circuit employsdifferential open-loop architecture, very linear source follower inputbuffers, NMOS sampling switches and bootstrap sampling-switch drivercircuits for high-speed operation with 3.3 V supply voltage. SPICEsimulations with MOSIS 0.35 m CMOS BSIM3v3 parameters showed thatit achieves a signal-to-(noise+distortion)-ratio (SNDR) of morethan 50 dB for up to 100 MHz sinusoidal input at 200 MS/s with 40 mWpower consumption. 相似文献