Improving path delay testability of sequential circuits

We analyze the causes of low path delay fault coverage in synchronous sequential circuits and propose a method to improve testability. The three main reasons for low path delay fault coverage are found to be: (A) combinationally false (nonactivatable) paths; (B) sequentially nonactivatable paths; and (C) unobservable fault effects. Accordingly, we classify undetected faults in Groups A, B, and C. Combinationally false paths ran be made testable by modifying the circuit or resynthesizing the combinational logic as discussed by other researchers. A majority of the untestable faults are, however found in Group B, where a signal transition cannot be functionally propagated through a combinational path. A test requires two successive states necessary to create a signal transition and propagate it through the target path embedded in the sequential circuit. We study a partial scan technique in which flip-flops are scanned to break cycles and shun that a substantial increase in the coverage of path delay faults is possible     

A rated-clock test method for path delay faults

Current test generation algorithms for path delay faults assume a variable-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan sequential circuit testing is impractical. A rated-clock path delay simulator shows a large drop in coverage for vectors obtained from existing test generators that assume a variable clock. A new test generation algorithm provides valid tests for uniform rated-clock test application. In this algorithm, signals are represented for three-vector sequences. The test generation procedure activates a target path from input to output using the three-vector algebra. For an effective backward justification, we derive an optimal 41-valued algebra. This is the first time, rated-clock tests for large circuits are obtained. Results for ISCAS-89 benchmarks show that rated-clock tests cover some longest, or close to longest, paths     

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

We propose a new path delay fault model called the transition path delay fault model. This model addresses the following issue. The path delay fault model captures small extra delays, such that each one by itself will not cause the circuit to fail, but their cumulative effect along a path from inputs to outputs can result in faulty behavior. However, non-robust tests for path delay faults may not detect situations where the cumulative effect of small extra delays is sufficient to cause faulty behavior after any number of extra delays are accumulated along a subpath. Under the new path delay fault model, a path delay fault is detected when all the single transition faults along the path are detected by the same test. This ensures that if the accumulation of small extra delays along a subpath is sufficient to cause faulty behavior, the faulty behavior will be detected due to the detection of a transition fault at the end of the subpath. We discuss the new model and present experimental results to demonstrate its viability as an alternative to the standard path delay fault model. We describe an efficient fault simulation procedure for this model. We also describe test generation procedures. An efficient test generation procedure we discuss combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.     

Resynthesis of combinational logic circuits for improved path delayfault testability using comparison units

We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparison unit if it implements a function belonging to the class of comparison functions defined here. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for resynthesis to improve the path delay fault testability of a circuit. Experimental results demonstrate considerable reductions in the number of paths and increased path delay fault testability. These are achieved without increasing the number of gates, or the number of gates along the longest path in the circuit. The random pattern testability for stuck-at faults remains unchanged     

On Selecting Testable Paths in Scan Designs

We propose an efficient method to select a minimal set of testable paths in scan designs, such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). The proposed path selection approach is based on a stepwise path expansion procedure that uses delay information and compact information about untestable paths to select longest paths while avoiding untestable paths. Techniques called delay analysis and delay-constrained path expansion are used to speedup the selection of paths to test. Compared to earlier approaches, the proposed approach is fast and it is guaranteed to find testable paths. Additionally the procedure also derives tests for the selected paths. Experimental results for ISCAS89 benchmark circuits using standard scan and broadside testing are presented to demonstrate the effectiveness of the proposed method.     

A fuzzy model for path delay fault detection

A fuzzy model is proposed to analyze the effectiveness of test pairs targeting path delay faults. This model is accurate enough to rank nonrobust tests by accounting for conditions not considered in existing models. It remains fully consistent with the traditional test robustness analysis. Finally, it also provides a coverage metric to be used to rank whole test sets. The proposed model has been implemented in a logic level path delay fault simulator. Its accuracy has been validated, for a set of combinational benchmarks, by means of a Monte Carlo logic-level event-driven path delay fault simulator.     

Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

Path delay fault model is the most suitable model for detectingdistributed manufacturing defects which can cause delayfaults. However, the number of paths in a modern design can beextremely large and the path delay testability of many practicaldesigns is very low. In this paper we show how to resynthesize acombinational circuit in order to reduce the total number of paths inthe circuit. Our results show that it is possible to obtain circuitswith a significant reduction in the number of paths while notincreasing area and/or delay of the longest sensitizable path in thecircuit.Research on path delay testing shows that in many circuits a largeportion of paths does not have a test that can guarantee detection ofa delay fault. The path delay testability of a circuit would increaseif the number of such paths is reduced. We show that addition of asmall number of test points into the circuit can help reducing thenumber of such paths in the given design.     

Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits

We present a technique to statistically estimate path-delay fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multivalue algebra and accumulate signal transition statistics, from which we calculate controllabilities of all signals and sensitization probabilities for all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all-paths method, or by a nonenumerative method considering only the longest paths. The path-delay fault detectability is the product of observabilities of signals on paths from primary inputs (PIs) or pseudo-primary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs (PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with exact fault simulation, the average absolute deviation in our statistical fault coverage estimation technique is 1.23% and the very worst absolute deviation was 6.59%. On average, our method accelerates delay fault coverage computation four times over an exact path delay fault simulator.     

Oscillation Ring Delay Test for High Performance Microprocessors

This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors.     

双倍可变观测点的时滞测试

随着高速集成电路的发展,对时滞测试的研究越来越重要了,时滞测试的主要困难来自于与电路的门数成指数增长的庞大通路数,以及大量的时滞不可测通路。本文提供了一种使用双倍可变观测点进行时滞测试的方法,保证了只需要测试少量通路就能完成整个电路的时滞测试,它所付出的代价是：对每一个测试向量对,测试仪需要在原始输出采样两次以确定预期跳变的传输时间,此方法所需测试的通睡数与被测电路的门数成线性增长关系,从而很大程     

Delay Fault Coverage Enhancement Using Variable Observation Times

Detection of system timing failures has become a very importantproblem whenever high speed system operation is required. It has beendemonstrated that delay fault coverage loss could be significant if improperpropagation paths are used. This occurs when the delay test pair of a targetpropagation path cannot be effectively generated by an ATPG tool, or whenstuck-at test patterns are used as transition (or gate) delay test patterns.In this work, an efficient method is proposed to reduce the amount of faultcoverage loss by using variable observation times. The basic idea is tooffset the shorter propagation paths (really used) by tightening theobservation times. Given a probability distribution of defect sizes and aset of slack differences, this method is able to locate several observationtimes that result in small fault coverage loss.     

False-Path Removal Using Delay Fault Simulation

Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All segments of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a non-enumerative path delay fault simulator based on the path status graph (PSG) data-structure, which duplicates selected gates to separate the detected and undetected path delay faults. The expanded circuit may contain new redundant stuck-at faults, corresponding to those undetected paths that are false. This happens because the expanded circuit has some new interconnects with only false paths passing through them. Such links become the sites for redundant stuck-at faults. Removal of these redundant faults eliminates false paths. The reported results show that the quality of the result may depend on the coverage of testable paths by the vectors that are simulated. When non-enumerative path delay simulation and implication-based redundancy removal techniques are used, the present procedure of false-path elimination can be applied to very large circuits.     

Implicit deductive fault simulation for complex delay fault models

This paper introduces an implicit version of the well-known deductive fault simulation technique suitable to delay fault models with an exponential number of faults. The proposed method calculates the fault coverage by generating lists of entities for each line during a single topological circuit traversal. Each stored entity only contains a number and a subset of the test vectors. No delay faults are stored, and no special data structures are required. There are significant differences between the presented implicit method and fault coverage using deductive fault simulation. The method is shown to be effective for delay the path and segment delay fault models.     

Cell delay fault testing for iterative logic arrays

C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only if an input transition can not be propagated to the cell's output through a path in the cell in a specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all the paths in a cell is first derived, and then necessary conditions for sending this test set to each cell in the array and simultaneously propagating the fault effects to the primary outputs are given. Test set minimization can be solved in a similar way as for the fault cover problem. We use the pipelined array multiplier as an example, and show that it is C-testable with 214 two-pattern tests. With a small number of additional patterns, all the combinational faults can be detected pseudoexhaustive.     

Statistical estimation of delay fault detectabilities and fault grading

In this paper we present a technique to statistically estimate transition delay and path delay fault coverage. The basic method is an extension of STAFAN to include delay faults. By partitioning a combinational circuit into non-overlapping fanout free logic cones, we accurately calculate the transition sensitization controllabilities of 0 1 and 1 0 transitions of the lines within a fanout free logic cone to the output of the fanout free logic cone for each fanout free logic cone. A strategy to calculate the transition observabilities of fanout stems is proposed. The detectability of a path delay fault is evaluated as the product of the observabilities of the input line to its head gate within each fanout free logic cone on the path multiplied by the transition controllability of the path. When compared with the fault simulations, the estimations of transition delay fault coverage are within 2.3%. Also, the technique gives reasonably good path delay fault coverage estimation for large fault set of the ISCAS85 benchmark circuits.     

Path delay fault simulation of sequential circuits

To analyze path delay faults in synchronous sequential circuits, stimuli are simulated in a dual-vector mode. The signal states represent the logic and transition conditions for two consecutive vectors. After the simulation of each vector, only the activated paths are traced and the corresponding fault effect, if propagated to a flip-flop, is added to its fault list. A path numbering scheme avoids storage of path data which can be generated, if needed, from the path number. The simulation is independent of the specific delays of the combinational elements, and either robust or nonrobust detection can be simulated as options to the user. For robust simulation, an update rule for state variables is proposed whereby a flip-flop is updated with its correct value, provided it is a destination of at least one robustly activated path. This rule gives a higher and more realistic coverage of robustly detected faults. Experimental results verify the effectiveness of the simulator     

Reduction of Number of Paths to be Tested in Delay Testing

Delay testing is important for high speed ICs. The main difficulty in delay testing comes from the huge number of paths and the large percentage of delay untestable paths. Therefore, it is critical to reduce the number of paths to be tested in delay testing. This paper presents two approaches to delay testing with significant reduction of number of paths to be tested, which provide high path delay fault coverage by testing a small number of paths. In the first approach, it is necessary to sample the primary output twice, one before and another after the transition for each test pair. The second approach is by means of accurate measurement of delays of very limited number of paths. In order to make this approach feasible, the paper also introduces a new concept of path sensitization, termed single-transition sensitization, to allow direct measurement of propagation delay of those paths. The paper presents how to select the very limited number of paths, termed sample paths, and how to generate test pairs and observation times for the sample paths for the first approach. On the other hand, it is noted for the second approach that under the analytical delay model (Proc. 9th International Conf. on VLSI Design, Bangalore, India, Jan. 1996, pp. 162–165), most of the paths are delay testable, which makes the accurate measurement approach feasible. In fact, it would be very difficult to select sample paths based on single path sensitization as it was done in (IEEE Trans. on Computers, Vol. c-29, No. 3, pp. 235–248, March 1980). The paper shows that the number of sample paths is linear to the number of gates in the circuit under test, despite exponential growth in the number of single paths.     

Selection of test paths for solder joint intermittent connection faults under DC stimulus

The test path of solder joint intermittent connection faults under direct-current stimulus is examined in this paper. According to the physical structure of the circuit, a network model is established first. A network node is utilised to represent the test node. The path edge refers to the number of intermittent connection faults in the path. Then, the selection criteria of the test path based on the node degree index are proposed and the solder joint intermittent connection faults are covered using fewer test paths. Finally, three circuits are selected to verify the method. To test if the intermittent fault is covered by the test paths, the intermittent fault is simulated by a switch. The results show that the proposed method can detect the solder joint intermittent connection fault using fewer test paths. Additionally, the number of detection steps is greatly reduced without compromising fault coverage.     

Hierarchical Delay Test Generation

Delay testing is used to detect timing errors in a digital circuit.In this paper, we report a tool called MODET forautomatic test generation for path delay faults in modular combinational circuits. Our technique usesprecomputed robust delay tests for individual modules to computerobust delay tests for the module-level circuit. We present alongest path theorem at the module level ofabstraction which specifies the requirements for path selectionduring delay testing. Based on this theorem, we propose a pathselection procedure in module-level circuits and report efficientalgorithms for delay test generation. MODET hasbeen tested against a number of hierarchical circuits with impressivespeedups in relation to gate-level test generation.     

Diagnosis Framework for Locating Failed Segments of Path Delay Faults

Diagnosis tools can be used to speed up the process for finding the root causes of functional or performance problems in a VLSI circuit. In this paper, we propose a method to locate possible segments that cause extra delays on circuit paths. We use the delay bounds of the tested paths to build linear constraints. By guiding the solutions of the linear constraints solved by a linear programming solver, we can identify segments with extra delays. Also, with the ranks of segment delays, we can prioritize the search for possible locations of failed segments. Besides, we also propose to reduce the search space by identifying indistinguishable segments. Essentially, we cannot separate segments in the same category no matter which segments have faults. This approach greatly increases the efficiency of the diagnosis process. Three main features of the proposed method are that: 1) it does not assume any delay fault model; 2) it derives diagnosis results directly from test data; and 3) it is able to diagnose failures caused by multiple delay defects. These features make our proposed method more realistic on solving the real problems occurring in the manufacturing process. In the experimental results, for most cases of injecting 5% of the longest path delay, the probabilities are over 90% for locating faulty segments within the list of top-ten suspects, and the average rankings, that is often referred to as first hit rank (FHR), which is defined as the rank of the first hit of the defect in the ranking list, are among the top five suspect locations for single fault injection. In the experimental results of multiple faults injection, the average FHRs are also lower than 5 for all cases of injecting 1% of the longest path delay.