Thin-film quasi-SOI power MOSFET fabricated by reversed siliconwafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 mΩ·mm² and on-state breakdown voltage of 30 V     

A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET

For the first time, a novel device concept of a quasi-silicon-on-insulator (SOI) MOSFET is proposed to eliminate the potential weaknesses of ultrathin body (UTB) SOI MOSFET for CMOS scaling toward the 35-nm gate length, and beyond. A scheme for fabrication of a quasi-SOI MOSFET is presented. The key characteristics of quasi-SOI are investigated by an extensive simulation study comparing them with UTB SOI MOSFET. The short-channel effects can be effectively suppressed by the insulator surrounding the source/drain regions, and the suppression capability can be even better than the UTB SOI MOSFET, due to the reduction of the electric flux in the buried layer. The self-heating effect, speed performance, and electronic characteristics of quasi-SOI MOSFET with the physical channel length of 35 nm are comprehensively studied. When compared to the UTB SOI MOSFET, the proposed device structure has better scaling capability. Finally, the design guideline and the optimal regions of quasi-SOI MOSFET are discussed.     

A quasi-SOI power MOSFET for radio frequency applications formed byreversed silicon wafer direct bonding

A quasi-SOI power MOSFET for radio frequency (RF) applications was fabricated by reversed silicon wafer direct bonding (RSDB). Its breakdown voltage was more than twice that of the conventional SOI power MOSFET and its other dc characteristics were almost the same. Its maximum oscillation frequency was about 15% higher than that of the conventional SOI power MOSFET. The power-added efficiency (PAE) of the quasi- SOI power MOSFET was higher than the SOI one. It showed excellent PAE of 68% at a drain bias of 3.6 V     

Scaling constraints imposed by self-heating in submicron SOIMOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction     

源区浅结SOI MOSFET的辐照效应模拟

研究了源区浅结的不对称SOIMOSFET对浮体效应的改善 ,模拟了总剂量、抗单粒子事件 (SEU)、瞬时辐照效应以及源区深度对抗辐照性能的影响 .这种结构器件的背沟道抗总剂量能力比传统器件有显著提高 ,并且随着源区深度的减小 ,抗总剂量辐照的能力不断加强 .体接触不对称结构的抗SEU和瞬时辐照能力优于无体接触结构和传统结构器件 ,这与体接触对浮体效应的抑制和寄生npn双极晶体管电流增益的下降有关     

Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs

In this paper, the graded channel gate stack (GCGS) DG MOSFET structure is studied in view of increasing device performance and immunity to short channel effects. The device has the advantage of improved gate oxide reliability, suppressed parasitic bipolar effect, lower DIBL and higher cut-off frequency. Therefore, the device must be investigated with respect to the variation of different structure dependent parameters before fabrication to have better reliability and constancy. In this work we have studied the device with respect to variation in high K oxide thickness (t_oxh) and channel length (L_g) to have better understanding on variation of different analog/RF performance parameters. The results validate that variations in t_oxh of the device significantly alters device performance parameters and must be pre accounted for realizing reliable analog/RF system on chip circuits.     

Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI)MOSFET for deep sub-0.1-μm channel regime

This letter proposes a new device structure which is called the “partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET.” The PGP SOI MOSFET minimizes the short-channel effect (SCE) compared to the conventional single-gate (SG) SOI MOSFET because the gate-induced field in the SOI layer is held high by the PGP region. This results in a lower stand-by leakage current. The PGP SOI MOSFET also shows much better switching performance and extremely high analog performance because of its smaller parasitic capacitance compared to the conventional ground-plane (GP) device. Thus, it is shown that the PGP SOI MOSFET is a promising candidate for future deep-sub-0.1-μm mixed-mode LSIs     

Degradation in thin-film SOI MOSFET's caused by single-transistorlatch

The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and drain, the minimum drain voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the drain. Consequently, the maximum allowable drain voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET     

Body-contacted SOI MOSFET structure and its application to DRAM

A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFET's, the proposed SOI MOSFET's have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFET's have a fully bulk CMOS compatible layout and process     

Analysis and optimization of SDOI structure to maximize the intrinsic performance of extremely scaled MOSFETs

The advantages of using elevated S/D formed on oxide shallow trench isolation are studied in detail. By careful design, the short channel short channel effects can be suppressed by the elevated source/drain (S/D) structure. In addition, the S/D region parasitic capacitance is significantly suppressed by the silicon-on-insulator (SOI)-like S/D structure. Tradeoff between series resistance and gate-to-drain Miller capacitance can be achieved by carefully selecting the gate spacer thickness. With careful optimization of device geometry, both the gate-delay and power consumption can be significantly reduced together. Design guideline and potential performance gain with the S/D-on-insulator structure is discussed.     

Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed-Mode Applications

Schottky barrier MOSFETs have recently attracted attention as a viable alternative to conventional CMOS transistors for sub-65-nm technology nodes. An asymmetric Schottky tunneling source SOI MOSFET (STS-FET) is proposed in this paper. The Schottky tunneling source SOI MOSFET has the source/drain regions replaced with silicide as opposed to highly doped silicon in conventional devices. The main feature of this device is the concept of a gate-controlled Schottky barrier tunneling at the source. The device was optimized with respect to various parameters such as Schottky barrier height and gate oxide thickness. The optimized device shows excellent short channel immunity, compared to conventional SOI MOSFETs. The asymmetric nature of the device has been shown to improve the leakage current as well as the linear characteristics of the device as compared to conventional Schottky FETs. The STS-FET was fabricated, using conventional processes combined with the present NiSi technology and large angle implantation, and successfully demonstrated. The high immunity to short channel effects improves the scalability, and the output resistance of the device also makes it an attractive candidate for mixed-mode applications.      

Analysis of drain breakdown voltage in SOI n-channel MOSFETs

The reduction of drain breakdown voltage in SOI nMOSFETs with floating substrate is related to the presence of a parasitic n-p-n bipolar structure, the base of which is the floating body of the device. reduction of breakdown voltage (compared to the case where a body contact is used) is shown to be dependent on both channel length and minority carrier lifetime in the SOI material. Conversely, it is shown that mere measurement of MOSFET breakdown voltages can be used to extract the minority carrier lifetime in the SOI material.<>     

A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs

We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.     

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.     

High-current small-parasitic-capacitance MOSFET on a poly-Siinterlayered (PSI:Ψ) SOI wafer

A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO₂. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO₂/poly-Si/500-nm SiO₂) wafer. In this device, the highly concentrated p⁺ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages     

Body-contacted SOI MOSFET structure with fully bulk CMOS compatiblelayout and process

A new SOI MOSFET structure to reduce the floating body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The measured results show the suppressed floating body effect as expected. This new structure retains most of the advantages in the propagation delay of the conventional SOI MOSFET without body potential instability. An additional advantage of the proposed structure is that the layout and process are the same as those of bulk CMOS     

0.5μm部分耗尽SOI MOSFET中的寄生双极效应

0.5μm部分耗尽SOI MOSFET的寄生双极效应严重影响了SOI器件和电路的抗单粒子和抗瞬态γ辐射能力。文中显示,影响0.5μm部分耗尽SOI NMOSFET寄生的双极器件特性的因素很多,包括NMOSFET的栅上电压、漏端电压和体接触等,尤其以体接触最为关键。在器件处于浮体状态时,0.5μm SOI NMOSFET的寄生双极器件很容易被触发,导致单管闭锁。因此,在设计抗辐射SOI电路时,需要尽量降低SOI NMOSFET寄生双极效应,以提高电路的抗单粒子和抗瞬态γ辐射能力。     

全耗尽异质栅单Halo SOI MOSFET二维模型

为了抑制深亚微米SOI MOSFET的短沟道效应,并提高电流驱动能力,提出了异质栅单Halo SOI MOSFET器件结构,其栅极由具有不同功函数的两种材料拼接而成,并在沟道源端一侧引入Halo技术.采用分区的抛物线电势近似法和通用边界条件求解二维Poisson方程,为新结构器件建立了全耗尽条件下的表面势及阈值电压二维解析模型.对新结构器件与常规SOI MOSFET性能进行了对比研究.结果表明,新结构器件能有效抑制阈值电压漂移、热载流子效应和漏致势垒降低效应,并显著提高载流子通过沟道的输运速度.解析模型与器件数值模拟软件MEDICI所得结果高度吻合.     

Clarification of floating-body effects on drive current and shortchannel effect in deep sub-0.25 μm partially depleted SOIMOSFETs

We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 μm floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (V_th) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller V_th-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 μm, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current     

Single-event burnout hardening of planar power MOSFET with partially widened trench source

We present a single-event burnout (SEB) hardened planar power MOSFET with partially widened trench sources by three-dimensional (3D) numerical simulation.The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region (P-well region below the N+ source).The simulation result shows that the proposed structure can enhance the SEB survivability significantly.The critical value of linear energy transfer (LET),which indicates the maximum deposited energy on the device without SEB behavior,increases from 0.06 to 0.7 pC/μm.The SEB threshold voltage increases to 120 V,which is 80％ of the rated breakdown voltage.Meanwhile,the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure.Therefore,this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.