Hammerstein-Wiener system estimator initialization

In nonlinear system identification, the system is often represented as a series of blocks linked together. Such block-oriented models are built with static nonlinear subsystems and linear dynamic systems. This paper deals with the identification of the Hammerstein-Wiener model, which is a block-oriented model where a linear dynamic system is surrounded by two static nonlinearities at its input and output. The proposed identification scheme is iterative and will be demonstrated on measurements. It will be proven that on noiseless data and in absence of modeling errors, the optimization procedure converges to the true system locally.     

Specification and evaluation of polymorphic shellcode properties using a new temporal logic

It is a well-known fact that polymorphism is one of the greatest find of malicious code authors. Applied in the context of Buffer Overflow attacks, the detection of such codes becomes very difficult. In view of this problematic, which constitutes a real challenge for all the international community, we propose in this paper a new formal language (based on temporal logics such as CTL) allowing to specify polymorphic codes, to detect them and to better understand their nature. The efficiency and the expressiveness of this language are shown via the specification of a variety of properties characterizing polymorphic shellcodes. Finally, to make the verification process automatic, this language is supported by a new IDS (Intrusion Detection System) that will also be presented in this paper.     

Partial-predicate logic in computer science

Summary In A Logic Covering Undefinedness in Program Proofs [1], Barringer, Cheng and Jones present a 3-valued logic designed for Program-Verification and Computer Science applications in general. In this paper we want to add some the oretical background to their arguments for the need for such a system.     

Specification of communicating processes: temporal logic versus refusals-based refinement

In this paper we consider the relationship between refinement-oriented specification and specifications using a temporal logic. We investigate the extent to which one can check whether a program in a process algebra, such as Communicating Sequential Processes (CSP), satisfies a temporal logic specification using a refinement-based model checker, such as FDR. We consider what atomic formulae are appropriate in a temporal logic for specifying communicating processes, in particular where one wants to talk about the availability of events. We then show that, perhaps surprisingly, the standard stable failures model is not adequate for capturing specifications in such a logic: instead the refusal traces model must be used. We formalise the logic by giving it a semantics in this model. We show that the temporal operators eventually and until, and negation, cannot, in general, be tested for via simple refinement checks. For the remaining fragment of the logic, we present a translation into simple refinement checks. Finally, we show that refusal traces equivalence is characterised by a slightly augmented version of that fragment. M. J. Butler     

A bridge between constructive logic and computer programming

Some logic notions have their analogies among programming concepts and vice versa. But people often try to understand these analogies in too straightforward a manner. A collection of analogies arising between constructive logics and programming is summarized and illustrated here. Some examples of complexities usually not taken into account are shown.     

Smile: a computer program for partitioning of programmed logic arrays

This paper presents a new approach to optimal topological design of PLAs (programmed logic arrays). In particular we address the array partitioning problem and the implementation of partitioned arrays as block folded or parallel connected PLAs. We present a graph theoretic interpretation of the problem and an efficient heuristic algorithm. A computer program, Smile, is described and experimental results are reported.     

Adding a temporal dimension to a logic system

We introduce a methodology whereby an arbitrary logic system L can be enriched with temporal features to create a new system T(L). The new system is constructed by combining L with a pure propositional temporal logic T (such as linear temporal logic with Since and Until) in a special way. We refer to this method as adding a temporal dimension to L or just temporalising L. We show that the logic system T(L) preserves several properties of the original temporal logic like soundness, completeness, decidability, conservativeness and separation over linear flows of time. We then focus on the temporalisation of first-order logic, and a comparison is make with other first-order approaches to the handling of time.     

Specification and validation of a concurrent system: an educational project

For several years we have been in charge of a course on specification and validation of concurrent and reactive systems. At the end of this course, the students must carry out a project dealing with a model railway. They have to specify the railway, validate their model, and finally translate it into a program controlling the model railway with up to five trains. In this paper, after presenting the project, we describe how the railway is specified and checked, step by step, by the students. We also explain how the analysis results lead to a policy for the switch control. Finally, we include some remarks about the implementation. Published online: 24 August 2001     

OTTER experiments in a system of combinatory logic

This paper describes some experiments involving the automated theorem-proving program OTTER in the system TRC of illative combinatory logic. We show how OTTER can be steered to find a contradiction in an inconsistent variant of TRC, and present some experimentally discovered identities in TRC.This work was supported by the Office of Scientific Computing U.S. Department of Energy, under the Summer 1994 Faculty Research Participation Program at Argonne National Laboratory.     

A methodology for auto/manual logic in a computer controlled process

The usual methods of implementing the auto/manual logic in complex process oontrol systems hamper modularity and often lack a unified structure. In this paper we develop a language for describing the required logical procedures, based on the nature of the interdependencies which can exist between different control loops or functions in a system. A software structure is presented which implements the auto logic while retaining the autonomy and modularity of the control functions, and a simple example of its application is discussed.     

计算机专业硬件课程体系的改革

数字逻辑、计算机组成原理和计算机体系结构是计算机专业的三门相关的主干硬件课程。现有的课程体系中这三门课程相对独立,不符合当今技术的发展,尤其不适合需掌握完整的计算机设计技术的计算机专业的学生需求。结合十二五国家级示范实验教学中心的建设,复旦大学计算机学院对计算机专业的硬件类课程群进行重新规划,以满足计算机学科发展的要求。     

Specification of the JSM intelligent system

The problems of developing computer systems that perform intellectual analysis of empirical data in fields with weakly formalized knowledge are described. The JSM system for analysis of non-quantitative sociological data is presented as an example of the implementation of such a system.     

Integration of a security type system into a program logic

Type systems and program logics are often thought to be at opposing ends of the spectrum of formal software analyses. In this paper we show that a flow-sensitive type system ensuring non-interference in a simple while-language can be expressed through specialised rules of a program logic. In our framework, the structure of non-interference proofs resembles the corresponding derivations in a state-of-the-art security type system, meaning that the algorithmic version of the type system can be used as a proof procedure for the logic. We argue that this is important for obtaining uniform proof certificates in a proof-carrying code framework. We discuss in which cases the interleaving of approximative and precise reasoning allows us to deal with delimited information release. Finally, we present ideas on how our results can be extended to encompass features of realistic programming languages such as Java.     

Specification and analysis of system architecture using Rapide

Rapide is an event-based, concurrent, object-oriented language specifically designed for prototyping system architectures. Two principle design goals are: (1) to provide constructs for defining executable prototypes of architectures and (2) to adopt an execution model in which the concurrency, synchronization, dataflow, and timing properties of a prototype are explicitly represented. This paper describes the partially ordered event set (poset) execution model and outlines with examples some of the event-based features for defining communication architectures and relationships between architectures. Various features of Rapide are illustrated by excerpts from a prototype of the X/Open distributed transaction processing reference architecture     

A parallel logic system on a multicomputer architecture

This paper describes the implementation of a logic programming language on a massively parallel architecture. This implementation is based on the AND/OR Process Model which allows the exploitation of both AND and OR parallelism in logic programs. A distributed memory model is used, and a decentralized control mechanism has been designed. The multicomputer, which the system has been implemented on, consists of a network of Inmos Transputers. The AND/OR processes are implemented as Occam processes mapped onto the Transputer nodes. After the presentation of the system architecture and a deep discussion of the distributed memory management, some preliminary performance results are discussed.