A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads

A 25-ns 4-Mbit CMOS SRAM with 512 K word*8-bit organization has been developed. The RAM was fabricated using a 0.5- mu m double-poly and double-aluminum CMOS technology and was assembled in a 32-pin 400-mil DIP. A small cell size of 3.6*5.875 mu m/sup 2/ and a chip size of 7.46*17.41 mm/sup 2/ were obtained. A fast address access time of 25 ns with a single 3.3-V supply voltage has been achieved using the newly developed dynamic bit-line load (DBL) circuit scheme incorporated with an address transition detector (ATD), divided word-line structure (DWL), three-stage sense amplifier, and low-noise output circuit approach. A low operating current of 46 mA at 40 MHz and low standby currents of 70 mu A (TTL) and 5 mu A (CMOS) were also attained.<>     

A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology

A miniature Q-band low noise amplifier (LNA) using 0.13-/spl mu/m standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This three-stage common source thin-film microstrip LNA achieves a peak gain of 20dB at 43GHz with a compact chip size of 0.525mm/sup 2/. The 3-dB frequency bandwidth ranges from 34 to 44GHz and the minimum noise figure is 6.3dB at 41GHz. The LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain, highest output IP3, and smallest chip size.     

Design and analysis of novel high-gain and broad-band GaAs pHEMT MMIC distributed amplifiers with traveling-wave gain stages

Using the concept of traveling-wave gain stages, novel GaAs pseudomorphic high electron-mobility transistor monolithic-microwave integrated-circuit (MMIC) distributed amplifiers (DAs) are demonstrated to achieve high gain and over several octaves of bandwidth performance simultaneously for microwave and millimeter-wave frequency applications. The cascaded single-stage distributed amplifier (CSSDA) is used as traveling-wave gain stages to improve the gain performance of the conventional distributed amplifier (CDA). By adopting the low-pass filter topology between the CDA and CSSDA and tuning the gain shape of CDA and CSSDA separately, a broad-band and high-gain DA, called CDA-CSSDA-2, was accomplished. The detailed design equations are derived for the broad-band matching design of this CDA-CSSDA-2. Two other MMICs, namely, a two-stage CSSDA called 2-CSSDA, and another two-stage design called CDA-CSSDA-1, are also included in this paper. This CDA-CSSDA-2 achieves 22/spl plusmn/1.5-dB small-signal gain from 0.1 to 40 GHz with a chip size of 1.5/spl times/2 mm/sup 2/. It also produces a gain-bandwidth product of 503 GHz, which is the highest among all reported GaAs-based DAs. The flat group delay also demonstrates the feasibility of this design for future digital optical communications and broad-band pulse applications.     

级联型单级分布式宽带单片功率放大器

报道了一个采用级联型单级分布式结构的宽带单片功率放大器的设计方法和研制结果。文中通过拓扑比较和人工传输线理论研究,分析出该功放设计的难点,并基于仿真实验,给出解决方案。最终研制的两级单片功放在6～18GHz频率范围内线性增益13.5dB,平坦度±1dB,输入输出驻波比均小于2。全频带上,饱和输出功率为300～450mW,功率附加效率大于15%。该宽带单片功率放大器在100mm GaAs MMIC工艺线上采用0.25μm功率pHEMT标准工艺制作,芯片尺寸为2.7mm×1.25mm×0.08mm。     

A 32-GHz non-uniform distributed amplifier in 0.18-/spl mu/m CMOS

This letter presents a fully integrated distributed amplifier in a standard 0.18-/spl mu/m CMOS technology. By employing a nonuniform architecture for the synthetic transmission lines, the proposed distributed amplifier exhibits enhanced performance in terms of gain and bandwidth. Drawing a dc current of 45mA from a 2.2-V supply voltage, the fabricated circuit exhibits 9.5-dB pass-band gain with a bandwidth of 32GHz while maintaining good input and output return losses over the entire frequency band. With a compact layout technique, the chip size of the distributed amplifier including the testing pads is 940/spl times/860/spl mu/m/sup 2/.     

Micropower CMOS S&H circuit for ambient intelligence applications

A novel sample and hold (S&H) circuit is presented based on the use of a class AB CMOS operational transconductance amplifier with very high slew rate and very low static power consumption. The circuit has been fabricated in a 0.5 /spl mu/m double-poly CMOS technology. The quiescent power consumption is only 80 /spl mu/W using a dual supply voltage of /spl plusmn/1.35 V. The S&H occupies 0.075 mm/sup 2/ of silicon area.     

A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-/spl mu/m CMOS

A 24-GHz +14.5-dBm fully integrated power amplifier with on-chip 50-/spl Omega/ input and output matching is demonstrated in 0.18-/spl mu/m CMOS. The use of substrate-shielded coplanar waveguide structures for matching networks results in low passive loss and small die size. Simple circuit techniques based on stability criteria derived result in an unconditionally stable amplifier. The power amplifier achieves a power gain of 7 dB and a maximum single-ended output power of +14.5-dBm with a 3-dB bandwidth of 3.1 GHz, while drawing 100 mA from a 2.8-V supply. The chip area is 1.26 mm/sup 2/.     

120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs

A 1-Mbit CMOS full-featured EEPROM using a 1.0- mu m triple-polysilicon and double-metal process is described. The design is aimed at developing a manufacturable 120-ns 1-Mbit EEPROM with small chip size. Therefore, an advanced memory cell with high read current, an improved differential sensing technique, and an efficient ECC scheme are developed. The differential sensing amplifier utilizes the output of a current sensing amplifier connected to unselected memory as a reference level. The cell size is 3.8*8 mu m/sup 2/ and the chip size is 7.73*11.83 mm/sup 2/. The device is organized as either 128 K*8 or 64 K*16 by via-hole mask options. A 256-byte/128-word page-mode programming is implemented.<>     

GaAs Monolithic DC-6.4-GHz Variable-Gain Feedback Amplifier (Short Paper)

A GaAs dc-6.4-GHz variable-gain two-stage feedback amplifier with 11 dB gain has been developed. The wide bandwidth is achieved by combining a microwave matching circuit with a direct-coupled circuit. This design improves the bandwidth significantly. This circuit also has a reduced chip size. Since no interstage capacitor is necessary, the chip size is only 0.5 x 1.5 mm/sup 2/. Active resistance was used in the second stage feedback circuit for variable gain. Au/ WSi self-alignment technology with a 1-µm gate length was used to improve the high-frequency characteristics of the FET.     

CMOS/SOI 64Kb静态随机存储器

对一种CMOS/SOI 64Kb静态随机存储器进行了研究,其电路采用8K×8的并行结构体系．为了提高电路的速度,采用地址转换监控(Address-Translate-Detector,ATD)、两级字线(Double-Word-Line,DWL)和新型的两级灵敏放大等技术,电路存取时间仅40ns;同时,重点研究了SOI静电泄放(Electrostatic-Discharge,ESD)保护电路和一种改进的灵敏放大器,设计出一套全新ESD电路,其抗静电能力高达4200—4500V．SOI 64Kb CMOS静态存储器采用1.2μm SOI CMOS抗辐照工艺技术,芯片尺寸为7.8mm×7.24mm．     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process

This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D/sup 2/RAM fabricated by a 0.15-/spl mu/m standard CMOS process.     

A highly integrated analog front-end for 3G

This paper describes a reconfigurable analog front-end (AFE) and audio codec IC supporting the wideband code division multiple access (WCDMA) standard. The chip is fabricated on Intel's 0.18-/spl mu/m (SOC) flash+logic+analog (FLA) process technology using a 0.35-/spl mu/m feature size analog transistor. The transmit path contains a 10-bit segmented rail-to-rail digital-to-analog converter, automatically tunable active RC filter, and programmable gain amplifier (PGA) with self-tuning gain and offset correction circuit. The receive path incorporates a PGA, active RC filter, and an 8-bit analog-to-digital converter with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA and total active area of 15 mm/sup 2/.     

A 15-ns 1-Mbit CMOS SRAM

A 1-Mb CMOS static RAM with a 256 K word×4-bit configuration has been developed. The RAM was fabricated using 0.8-μm double-poly and double-aluminum twin-well CMOS technology. A small cell size of 5.2 μm×8.5 μm and a chip size of 6.15 mm×15.21 mm have been achieved. A fast address access time of 15 ns was achieved using novel circuit techniques: a PMOS-load decoder and a three-stage dynamic gain control sense amplifier combined with an equalization technique and feedback capacitances. A low active current of 50 mA at 20 MHz and low standby currents of 15 mA (TTL) and 2 μA (CMOS) were also attained     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

A 40-Gb/s Transimpedance Amplifier in 0.18-$mu$m CMOS Technology

A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology. From the measured S-parameters, a transimpedance gain of 51 dBOmega and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, pi-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 X 0.46 mm2. The proposed CMOS TIA presents a gain-bandwidth product per DC power figure of merit (GBP/P_de) of 180.1 GHzOmega/mW.     

A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-/spl mu/m CMOS technology

An ultra-wideband mixer using standard complementary metal oxide semiconductor (CMOS) technology was first proposed in this paper. This broadband mixer achieves measured conversion gain of 11 /spl plusmn/ 1.5 dB with a bandwidth of 0.3 to 25 GHz. The mixer was fabricated in a commercial 0.18-/spl mu/m CMOS technology and demonstrated the highest frequency and bandwidth of operation. It also presented better gain-bandwidth-product performance compared with that of GaAs-based HBT technologies. The chip area is 0.8 /spl times/ 1 mm/sup 2/.     

A 71–80 GHz Amplifier Using 0.13- μm CMOS Technology

A 71-80 GHz amplifier using 0.13-mum standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This four-stage cascade thin-film microstrip amplifier achieves the peak gain of 7.0 dB at 75 GHz. The 3-dB frequency bandwidth range is from 71 to 80 GHz. The amplifier demonstrates the highest amplification frequency and smallest chip size among previous published millimeter-wave (MMW) 0.13-mum CMOS amplifiers.     

0.9 V rail-to-rail constant gm CMOS amplifier input stage

Presented is a 0.9 V rail-to-rail constant g_m CMOS amplifier input stage consisting of complementary differential pairs and a g_m control circuit. The g_m control circuit eliminates the g_m dead zone, which occurs in the conventional rail-to-rail amplifier with ultra-low supply voltages. The proposed amplifier input stage has a constant g_m that varies by ±2.3% for rail-to-rail input common-mode levels. To verify the proposed amplifier design, an experimental prototype operational amplifier is also implemented using 0.35 mm standard CMOS technology.     

A coplanar X-band AlGaN/GaN power amplifier MMIC on s.i. SiC substrate

This work presents a two-stage high-power amplifier monolithic microwave integrated circuit (MMIC) operating between 9 GHz and 11 GHz based on a fully integrated AlGaN/GaN high electron mobility transistor (HEMT) technology on s.i. SiC substrate and is suitable for radar applications. The MMIC device with a chip size of 4.5/spl times/3 mm/sup 2/ yields a linear gain of 20 dB and a maximum pulsed saturated output power of 13.4 W at 10 GHz equivalent to 3.3 W/mm at V/sub DS/=35V, 10% duty cycle, and a gain compression level of 5 dB. Further, dc reliability data are given for the MMIC HEMT technology.