Wire Optimization for Multimedia SoC and SiP Designs

With advances in VLSI integration technology, a large number of hardware components can be integrated into a single chip. To provide the communication bandwidth for these components, existing bus-based interconnects often suffer from a large area occupied by a large number of bus signals. To address this issue, this paper proposes a new protocol for on-chip or in-package communication that is termed the System-on-Chip Network Protocol (SNP). SNP uses a small number of signals that are shared by address, control, and data information. Additional three-bit phase signals are used to distinguish the different information transmitted through a single set of SNP signals. Two sets of identical SNP signals form a symmetric communication channel that allow a master-to-master type of communication between hardware components. The phase signals facilitate the reduction of the communication time with phase interleaving and phase omission-restoration among successive transactions. The efficiency of SNP is evaluated by a static performance analysis as well as by simulations with register-transfer level models of SNP components. Both the analysis and simulation results show that the communication time with SNP is approximately a half that of Advanced Microcontroller Bus Architecture Advanced High-Performance Bus (AHB), although SNP has wires that are approximately three-fifths of AHB. MPEG-4 chips are implemented with both AHB and SNP, respectively, and it is observed from the MPEG-4 implementations that SNP requires less area for communication compared to AHB.      

高密度封装进展之三——SiP与SoC

哪种方式更能提高LST的附加值?是SiP(system in a package)还是SoC(system on a chip)?LSI厂家正对此进行激烈争论。作为系统集成的选择方式,LSI厂家一直集中力量致力于SoC的开发。但是LSI厂家发现,仅靠SoC这一条路线已不能满足用户的要求。目前,对于各大LSI厂家来说,要不要转换其发展资源的投入方向,需要当机立断。     

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors

A multicore system-on-chip (SoC) has been developed for various applications (recognition, inference, measurement, control, and security) that require high-performance processing and low power consumption. This SoC integrates three types of synthesizable processors: eight CPUs (M32R), two multi-bank matrix processors (MBMX), and a controller (M32C). These processors operate at 1 GHz, 500 MHz, and 500 MHz, respectively. These three types of processors are interconnected on this chip with a high-bandwidth multi-layer system bus. The eight CPUs are connected to a common pipelined bus using a cache coherence mechanism. Additionally, a 512-kB L2 cache memory is shared by the eight CPUs to reduce internal bus traffic. A multi-bank matrix processor with 2-read/1-write calculation and background I/O operation has been adopted. The 1-GHz CPU is realized using a delay management network which consists of delay monitors that can be applied for any kind of application or process technology. Our configurable heterogeneous architecture with nine CPUs and two matrix processors reduces power consumption by 45%.     

鱼与熊掌:SoC,还是SiP?

本文分析了SoC和SiP的各自特点,指出SiP是一种充满前途的芯片形式,但是缺乏标准和设计工具将制约SiP的成长.     

异构双核系统中多媒体应用的智能任务控制器

针对异构双核的嵌入式系统中MPU和DSP处理器间的频繁通信导致系统性能降低的问题,文中提出了一种适用于多媒体应用的智能任务控制器。该控制器可动态实现任务管理,并有效解决处理器间通信问题。文中采用ESL设计方法,构建双核处理器虚拟器平台,以像素为256×256的JPEG图像编码作为实际应用。结果表明,此智能控制器可减少15%~68%的任务管理时间。     

顺应高集成度发展趋势,SoC和SiP各显神通

在2000年前后的产业泡沫破灭之后,尽管需求和供给的天平时有变化,但半导体市场却始终面临一个僧多粥少的局面.半导体供应商为了在激烈的市场竞争中取得主动,不断投入巨资研发更先进的工艺,目标是提高芯片的性能,降低芯片的功耗,缩短产品设计时间,帮助客户在激烈的市场竞争中取得主动.高集成度显然是应对这一产业发展趋势的重要途径,不仅可以使系统设计更加容易,而且可以减少外围器件数量,降低总体物料成本.     

便携式多媒体SoC的视频处理方案

由于消费者对便携式多媒体设备的强劲需求及技术上的进步，设备制造商面对的挑战是必须把更多的功能和服务集成在越来越小型、价廉和功能多样化的产品中。要了解如何针对这个市场创建高价值及与众不同的多媒体SoC，我们必须先看看目前一般的便携式多媒体设备能够实现的技术范围。     

混沌密码及其在多媒体保密通信中应用的进展

该文回顾了过去混沌密码理论与应用的现状及存在的问题,并对其进行了综合评述。重点报道了近年来高维混沌密码及其在多媒体保密通信中的应用与硬件实现技术的进展,其中包括基本理论、设计方法、典型应用以及解决这些问题的思路。在混沌密码设计与安全性能评估方面,报道了以下几个方面的进展：基于反控制方法设计无简并高维混沌密码增强数字混沌的抗退化能力;无退化数字域混沌系统的设计;具有闭环反馈的有限精度高维混沌长周期序列流密码的多轮加密设计方案;高维混沌密码的安全性能评估。在多媒体保密通信中的应用与硬件实现方面,报道了针对手机,计算机,ARM, FPGA, DSP等手持设备所需不同应用业务、广域网和WIFI无线通信网传输的实时远程混沌保密通信应用环境和多位一体的应用平台进行优化融合,创建示范验证系统等若干技术实现问题的进展。该文试图推进国内外未来混沌密码理论及其应用的研究。     

一种安全SoC芯片的物理设计

本文介绍了一种安全SoC芯片架构,描述了物理设计的指标要求及其在0．13umGSMCCMOS工艺上的物理设计,重点阐述了物理设计的中的3个关键技术——时序收敛设计、低功耗设计以及IO规划设计,并探讨了安全芯片物理设计上的自身安全性设计考虑。通过签核级的分析,该芯片最终满足了指标要求。该芯片包含36个时钟域,4种低功耗工作模式,约有26万个标准单元,72个宏模块,130个pad,合计约560万个逻辑等效门,芯片面积5．6mm×5．6mm。     

多通道阵列信号处理可重构异构SoC设计

设计实现了面向多通道阵列信号处理的可重构异构SoC。SoC集成了多通道阵列信号处理需要的多个硬件加速模块,有效提高了多通道阵列信号处理系统的计算能力。通过软件对各个算法模块的输入输出流向进行重构,达到了多通道阵列信号处理算法可重构的目的,扩展了SoC的适用范围。采用55 nm工艺进行设计,版图尺寸为6.2 mm×4.5 mm,规模约为1 000万门。流片后的测试结果验证了多通道阵列信号处理算法的有效性,证明了SoC设计的正确性。     

SoC and SiP, the Yin and Yang of the Tao for the New Electronic Era

“More than Moore” is becoming the password for these coming years. New steps to overcome technology limitations to diffuse, on the same die, different chips to have a complete system have been developed. This approach is called system in package (SiP), a way to have in a package dies of logic, analog, memory, passive components, etc., assembled to obtain a miniaturized board. SiP performances and limitations are here analyzed to understand advantages versus system on chip (SoC). This paper is a discussion about the main items that can lead to the choice of the right approach—SiP or SoC—before a system design start. Three persons attend to our virtual meeting: an SoC technology development manager, expert in microcontroller embedded memories and technology integration; an SiP analog radio-frequency design senior expert; and a moderator that designed embedded memories and now SiP, all involved to understand how to reach a tradeoff among these two approaches. Like for the Yin and Yang, symbol of the equilibrium for the Taoist philosophy, the two opposites divide the circle of the life, with a piece of each in the other.      

A Low-Dropout Regulator for SoC With Q-Reduction

A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (V_THN ap 0.55 V and |V_THP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current     

AMD向异构多核处理器迈出第一步

从2004年下半年起,AMD和Intel这两大主流处理器供应商开始向多核处理器进军.两家公司尽可能在芯片上集成更多的处理核,同时简化设计减少系统功耗并提高整体性能.多核处理器的实质是在同一芯片中集成很多同样的处理核.这一方法降低了设计的复杂性,减小了处理节点,并成为多核处理器发展的一种趋势-这种趋势显然对于服务器应用来说更合适,因为服务器通常为多用户提供固定且有限的功能.     

系统模块(SiP)和三维封装(3D)在移动通讯中的应用

电子封装业界正遭受着前所未有的来自手机和其他移动通讯终端设备挑战。在这一领域里,IC封装的关键是尺寸微型化,缩减成本和市场时机。这一挑战的背后隐含着手机技术发展的两大趋势:系统模块化和日益增长的复杂性及功能。越来越多的功能正在被组合到手机上即PDA、MP3、照相机、互联网等等。功能的增加需要靠模块化来实现,而模块化又促进了更多功能的组合。同时,模块化使得移动通讯终端设备得以微型化、降低成本和缩短设计周期。业界越来越多地感受到整体射频模块和通讯模块解决方案的必要性。这些整体模块把手机设计师从电路设计的细节中解脱出来,从而能专著于高层的手机应用和系统的设计。为了满足上诉移动通讯产品的苛刻要求,大量的新兴电子封装技术和封装产品应运而生。最引人注目的例子在于对系统模块穴SiP雪和三维穴3D雪封装的重点资金和技术投入。这两项先进封装技术有着各自不同的特征和应用范围。总体介绍先进封装技术在移动通讯中的应用,重点讨论电子封装材料和工艺所面临的挑战和最新发展趋势。对移动通讯带来的新一轮集成化及其所产生的潜在供应链问题也做了适当的讨论。     

异构双核SoC设计与实现

异构双核SoC采用SPARC V8处理器加专用DSP的架构,根据其应用特点,设计了SPARC V8处理器与专用DSP之间互斥通讯机制。并完成了SPARC V8处理器的状态控制设计与优化、外部存储控制器的接口优化设计,以及SoC的整体功能验证。FPGA实验结果表明,异构双核SoC功能正确可靠,有效地提高了系统的效能比。     

HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing

The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell CMOS technology, occupies about 81 mm², and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.From 1995 to 1996, he was with the NEC Information Technology Research Laboratories, Kawasaki, Japan, working on efficient implementations of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization for signal processing and multimedia applications.Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.Sören Moch received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1997.Since then he has been Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of processor architectures for image, video and multimedia signal processing applications.Lars Friebe studied electrical engineering at the Universities Ulm and Hannover, Germany. In 1999, he worked at the NEC System ULSI Research Laboratory in Kanagawa, Japan. He received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1999.Since then he has been a Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of parallel programmable VLSI architectures for real-time image processing.Mark B. Kulaczewski started his studies in electrical engineering at the University of Hannover, Germany. In 1994, he transferred to Purdue University, West Lafayette, USA, and received the M.S. degree in electrical engineering in 1996.Since 1997 he has been a Research Assistant at the Laboratory for Information Technology and the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable real-time architectures for video coding and image segmentation, and instruction-set extensions for cryptographic applications.Sebastian Flügel was born in Crivitz, Germany, in 1975. He received his Dipl.-Ing. degree from the Department of Electrical Engineering of the University of Rostock in 2001.Since then he has been a Ph.D. candidate at the Institute of Microelectronic Systems at the University of Hannover. He works in the field of architectures and systems for video processing systems. His focus is on algorithms for video encoding and the development of optimized hardware architectures.Heiko Klußmann received the Dipl.-Ing. degree in computer engineering from the University of Hannover, Germany, in 2002.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests are in the area of programmable architectures for real-time video signal processing.Andreas Dehnhardt was born in Frankfurt am Main, Germany, in 1976. He received his Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 2002.Since then, he has been a Research Assistant with the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable architectures for multimedia applications and implementation of real-time MPEG-4 encoding schemes.Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1980 and in Summer 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL research center, Stuttgart. Since 1987 he is Professor in the Department of Electrical Engineering, since 2002 in the Department of Computer Science at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002. His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.     

C++ Support and Applications for Embedded Multicore DSP Systems

In recent years embedded systems have entered the multicore era. As the number of cores keeps growing in embedded systems, it becomes more important to provide programming support which considers embedded system constraints and in the meanwhile helps utilize multicore systems. So far though C still dominates embedded programming, C++ is gaining in importance in parallel programming. It is promising to support C++ for embedded multicore systems. However, embedded systems usually have tight resource budgets, and C++ is commonly considered having huge code size that embedded systems can not afford. Therefore, in this paper we investigate the code size requirement of a C++ library and propose a layered design to provide a code size aware library support. On the other hand, to utilize embedded multicore systems, we employ C++ linguistic features to facilitate embedded multicore programming. With C++, we incorporate high-level abstractions and design patterns into the programming support to enhance low-level programming APIs that can be used to exploit DSPs, SIMD instructions, and DMAs on embedded multicore systems. At last, we evaluate our C++ support with a Blur and a JPEG program. Our result on a dual-DSP platform shows that we can obtain speedups of 3.32 and 3.09 for the Blur and JPEG program, respectively.     

一种异构双核SoC的抗SEU加固方案

异构双核SoC结构复杂,不同部分受到单粒子翻转(SEU)的影响程度不同。采用单一的技术对整个SoC进行加固,既浪费资源,效果也不好。根据不同部分受SEU影响的不同特点,选取SoC中受SEU影响最大的几个部分进行优化加固。使用自动三模冗余添加技术对处理器的寄存器堆和取指通道进行了加固,使用汉明码对存储器进行了加固,使用软硬协同的软件签名技术对CPU运行的程序进行了检测,不会对CPU的性能产生影响。仿真和物理实现的结果表明,相对于未加固的设计,该方案抗SEU能力提高了6倍,与全加固设计的抗SEU能力相当。该方案的面积消耗仅为34%,而全加固的为88%。     

可证安全的IDPKC-to-CLPKC异构签密方案

为了保证异构网络中消息的机密性和认证性,该文定义了身份公钥密码IDPKC到无证书公钥密码CLPKC异构签密模型,并提出具体的IDPKC-to-CLPKC异构签密方案。方案中双方密码系统参数相互独立,能够满足实际应用需求。在随机预言模型下,基于GBDH, CDH和q-SDH困难假设,证明方案满足IDPKC-to-CLPKC异构签密的机密性和不可伪造性。同时,该方案满足匿名性,通过密文无法判断发送方和接收方的身份,可以有效保护双方的身份隐私。     

支持移动多媒体的安全中间件

安全以其复杂性和高计算性成为移动通信和移动Internet、特别是移动电子商务发展的瓶颈。根据中间件屏蔽复杂性的特性,设计了一种支持移动多媒体通信的安全中间件模型。该模型主要实现2大安全性服务:基于3GPP标准建议实现移动终端和移动网络的安全通信,在此基础上基于WAP2.0标准实现移动终端与Internet等第3方服务提供商之间的安全通信。主要描述和分析了这个安全中间件模型,并在此基础上提出了一种实现移动终端到移动终端的端到端通信安全的方法。