Fast modeling of core switching noise on distributed LRC power gridin ULSI circuits

As technology scales, power supply noise caused by core logic switching becomes critical. Shorter signal rise edge, high integration density, and necessity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with millions of switching devices. In this paper, we propose a sophisticated power grid model consisting of distributed LRC elements excited by constant voltage sources and switching capacitors. Based on this, fast equations for core switching noise estimations were formulated. Full-chip noise distribution on the power grid with any topology was efficiently and accurately computed. SPICE simulations confirmed its efficiency and accuracy. Experimental results obtained on our benchmark circuits revealed that the proposed technique speeded up simulations by several orders of magnitude compared with SPICE, whereas typical relative error was between 0±5%. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power noise. Meanwhile, locations of hot spots in the power network are precisely identified. The model is suitable for full-chip rapid simulations for on-chip power distribution design in advanced ultra large scale integration (ULSI) circuits, particularly for early stage analysis, in which global and local optimization such as topology selection, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted     

MOSFET衬底电流模型及参数提取

在短沟道ＭＯＳＦＥＴ器件物理的基础上,导出了其衬底电流解析模型,并通过实验进行了模型参数提取。模型输出与短沟ＭＯＳＦＥＴ实测结果比较接近,可应用于ＶＬＳＩ／ＵＬＳＩ可靠性模拟与监测研究和亚微米ＣＭＯＳ电路设计。     

Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter

Rotary clock is a resonant clocking technique that delivers on-chip clock signal distribution with very low power dissipation. Since it can only generate clock signals with multiple phases that are spatially distributed, rotary clock is often considered not applicable to industrial very large scale integration (VLSI) designs. This paper presents the first rotary-clock-based nontrivial digital circuit. Our design, a low-power and high-speed finite-impulse response (FIR) filter, is fully digital and generated using CMOS standard cells in 0.18 mum technology. We have shown that the proposed FIR filter is seamlessly integrated with the rotary clock technique. It uses the spatially distributed multiple clock phases of rotary clock and achieves high power savings. Simulation results demonstrate that our rotary-clock-based FIR filter can operate successfully at 610 MHz, providing a throughput of 39 Gb/s. In comparison with the conventional clock-tree-based design, our design achieves a 34.6% clocking power saving and a 12.8% overall circuit power saving. In addition, the peak current consumed by the rotary-clock-based filter is substantially lower by 40% on the average. Our study makes the crucial step toward the application of rotary clock technique to a broad range of VLSI designs.     

An analytical transient model for a 1.5 V BiCMOS dynamic logiccircuit for low-voltage deep submicrometer BiCMOS VLSI

This paper presents an analytical transient model for the 1.5 V BiCMOS dynamic logic circuit using Gummel-Poon charge control model for deep submicrometer BiCMOS VLSI. Based on the analysis, the switching time of the 1.5 V BiCMOS dynamic circuit is sensitive to the forward transit time with a large load capacitance. With a small load capacitance, its switching time is related to the threshold voltage     

VLSI scaling methods and low power CMOS buffer circuit

Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.     

用于测试CMOS输出驱动器电流变化率的新电路

提出了一种新的用于测试 CMOS输出驱动器电流变化率的电路结构 .它把片上电感引入到测试系统中作为对实际封装寄生电感的等效 ,从而排除了测试时复杂的芯片 -封装界面的影响 .这种电路结构不仅可以用于实际测算输出驱动器的性能指标 ,还可以用于研究 VL SI电路中的同步开关噪声问题 .该设计方法在新加坡特许半导体公司的 0 .6μm CMOS工艺线上进行了流片验证 .测试结果表明 ,这一测试结构能有效地表征 CMOS输出驱动器的电流变化率的性能指标和 VL SI电路中的同步开关噪声特性     

降压变换器片内集成软启动电路设计

针对电流模降压变换器的集成化趋势,提出了一种可片内集成的软启动电路. 该结构利用芯片振荡器产生的窄脉冲信号,控制微电流对片内电容间歇充电得到斜坡电压,并巧妙地利用复合比较器以较小的功耗实现了对峰值电流的限制,避免了浪涌电流,完成了软启动功能. 提出的软启动电路结构简单、易于实现,减少了芯片引脚数目,降低了PCB面积,并在一款基于0.5μm CMOS工艺设计的降压型DC-DC中进行了投片验证. 测试结果表明,3.6V输入1.8V输出600mA负载电流在使能140μs后芯片成功实现了软启动.     

Progress in the methodologies for the electrical modeling ofinterconnects and electronic packages

The rapid growth of the electrical modeling and analysis of the interconnect structure, both at the electronic chip and package level, can be attributed to the increasing importance of the electromagnetic properties of the interconnect circuit on the overall electrical performance of state-of-the-art very large scale integration (VLSI) systems. With switching speeds well below 1 ns in today's gigahertz processors, and VLSI circuit complexity exceeding the 100 million transistors per chip mark, power and signal distribution is characterized by multigigahertz bandwidth pulses propagating through a tightly coupled three-dimensional wiring structure that exhibits resonant behavior at the upper part of the spectrum. Consequently, in addition to the inductive and capacitive coupling, present between adjacent wires across the entire frequency bandwidth, distributed electromagnetic effects, manifested as interconnect-induced delay, reflection, radiation, and long-range nonlocal coupling, become prominent at high frequencies, with a decisive impact of overall system performance. The electromagnetic nature of such high-frequency effects, combined with the geometric complexity of the interconnect structure, make the electrical design of today's performance-driven systems extremely challenging. Its success is heavily dependent on the availability of sophisticated electromagnetic modeling methodologies and computer-aided design tools. This paper presents an overview of the different approaches employed today for the development of an electromagnetic modeling and simulation framework that can effectively tackle the complexity of the interconnect circuit and facilitate its design. In addition to identifying the current state of the art, an assessment is given of the challenges that lie ahead in the signal integrity-driven electrical design of tomorrow's performance- and/or portability-driven, multifunctional ULSI systems     

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.     

Analysis of inverse E class power amplifier with finite DC feed in sub-nominal condition

In this work an inverse E power amplifier with finite DC feed in sub-nominal condition is discussed. In the conventional inverse E the DC feed inductor is considered very large which imposes some conditions to the circuit such as constant current drawn from voltage supply and also a large value for inductance is hard to implement on-chip so this work removes the very large condition from DC feed inductance and proposes a finite DC feed for the structure and extracts the circuit parameters and design equations with regards to this matter. Furthermore to achieve a flexible design this work uses the phase shift between input and output voltages to control efficiency, peak switch voltage and peak switch current then the value of circuit elements and the tradeoffs for every choice are discussed in details and a design guideline is presented for achieving different goals in a finite DC feed inverse E PA. Finally the circuit is simulated in the 0.18 µm CMOS technology and the results are being verified.     

A 533-MHz BiCMOS superscalar RISC microprocessor

This 533-MHz BiCMOS very large scale integration (VLSI) implementation of the PowerPC architecture contains three pipelines and a large on-chip secondary cache to achieve a peak performance of 1600 MIPS. The 15 mm×10 mm die contains 2.7 M transistors (2M CMOS and 0.7 M bipolar) and dissipates less than 85 W. The die is fabricated in a six-level metal, 0.5-μm BiCMOS process and requires 3.6 and 2.1 V power supplies     

VLSI design investigation for low-cost, low-power FFT/IFFT processing in advanced VDSL transceivers

The problem of an efficient very large scale integration (VLSI) realization of the direct/inverse fast Fourier transform (FFT/IFFT) for digital subscriber line (DSL) applications is addressed in this paper. The design of scalable and very high-rate (VDSL) modem claims for large and high-throughput complex FFT computations while for massive and fast deployment of the xDSL family low-cost and low-power constraints are key issues. Throughout the paper we explore the design space at different levels (algorithm, arithmetic accuracy, architecture, technology) to achieve the best trade-off between processing performance, hardware complexity and power consumption. A programmable VLSI processor based on a FFT/IFFT cascade architecture plus pre/post-processing stages is discussed and characterized from the high-level choices down to the gate-level synthesis. Furthermore low-power design techniques, based on clock gating and data driven switching activity reduction, are used to decrease the power consumption exploiting the correlation of the FFT/IFFT coefficients and the statistics of the input signals. To this aim both frequency-division and time-division duplex schemes have been considered. The effects of supply voltage scaling and its consequence on circuit performance are examined in detail, as well as the use of different target technologies. Synthesis results for a 0.18 μm CMOS standard-cells technology show that the processor is suitable for real-time modulation and demodulation in scalable full-rate VDSL modem (64-4096 complex FFT, 20 Msample/s) with a power consumption of few tens of mW. These performances are very interesting when compared to state-of-the-art software implementations and custom VLSI ones.     

High-accuracy current sensing circuit with current compensation technique for buck–boost converter

A novel on-chip current sensing circuit with current compensation technique suitable for buck–boost converter is presented in this article. The proposed technique can sense the full-range inductor current with high accuracy and high speed. It is mainly based on matched current mirror and does not require a large proportion of aspect ratio between the powerFET and the senseFET, thus it reduces the complexity of circuit design and the layout mismatch issue without decreasing the power efficiency. The circuit is fabricated with TSMC 0.25 µm 2P5M mixed-signal process. Simulation results show that the buck-boost converter can be operated at 200 kHz to 4 MHz switching frequency with an input voltage from 2.8 to 4.7 V. The output voltage is 3.6 V, and the maximum accuracy for both high and low side sensing current reaches 99% within the load current ranging from 200 to 600 mA.     

Automatic Substrate Switching Circuit for On-Chip Adaptive Power-Supply System

In energy-aggressive dynamic voltage scaling techniques, adaptive on-chip power supply, which can provide variable voltage in a wide range, is highly demanded. However, potential leakage and latch-up problems arise, when the substrate biasing voltages of the transistors vary with the supply voltage. An automatic substrate switching circuit (ASSC) is thus presented in this paper, with accurate voltage comparison, fast transient response and small silicon area. Experimental results show that the circuit automatically and accurately switches 1.3-nF pMOS substrate at a switching speed of 1.1 V/mus, with a switching voltage range of 1.1 to 3.3 V. The tracking error in steady state is below 18 mV. Fabricated in a standard 0.35-mum n-well digital CMOS process, the ASSC circuit only requires 0.017 mm ² silicon areas, with a maximum static power of 116 muW.     

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for     

一种基于自适应峰值电流检测的模式切换电路北大核心

在降压转换器中，为了在不同的负载情况下获得高效率，常采用的方法是在重载时使用脉冲宽度调制(PWM),在轻载时使用脉冲频率调制(PFM),因此需要模式切换信号去控制整个降压转换器的工作状态，同时模式切换信号也可以用于自适应改变功率级电路中的功率管栅宽，减小功率管的栅极电容，提高整体电路的效率。文章设计了一个自适应峰值电流模式切换电路，用于产生模式切换信号，其原理是监控峰值电流的变化，产生峰值电压，将峰值电压与参考电压进行比较，得到模式切换信号，以决定降压转换器是采用PFM模式还是PWM模式。仿真结果表明，在负载电流0.5～500 mA范围内，该电路可以在两种调制模式之间平稳切换，其峰值效率可提升到94%以上。     

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.     

Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates

Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient IR voltage drops within a power distribution network. These transient IR voltage drops can affect the propagation delay of a CMOS logic gate, creating delay uncertainty within data paths. Analytical expressions characterizing these transient IR voltage drops are presented in this paper. The peak value of these transient IR voltage drops is within 6% as compared to SPICE. Circuit- and layout-level design constraints are also discussed to manage the peak value of the transient IR voltage drops. The propagation delay of a CMOS logic gate based on these analytical expressions is within 5% of SPICE while the estimate without considering transient IR voltage drops can exceed 20% for a 20 power line.     

On-chip CMOS current-sensing circuit for DC-DC buck converter

An on-chip CMOS current-sensing circuit for a DC-DC buck converter is presented. The circuit can measure the inductor current through sensing the voltage of the switch node during the converter on-state. By matching the MOSFETs, the achieved sense ratio is almost independent of temperature, model and supply voltage. The proposed circuit is suitable for low power DC-DC applications with high load current.     

A modified model of the light amplifying optical switch (LAOS)

A new analytical circuit model of the light amplifying optical switch (LAOS) is proposed. The static I-V curve, the switching voltage, and the input-output characteristics can be calculated from this model. The model is based on deriving an expression for the nonlinear current gain of the heterojunction phototransistor (HPT). The switching mechanism and the I-V characteristics of the LAGS is studied in the context of optical and/or electrical feedback. The nonlinear current gain of the HPT, and the Early effect are the main factors which are responsible for the thyristor-like characteristics of the LAOS. An external feedback resistor is also added to achieve the appropriate switching condition and build up the feedback mechanism. A bistable system using a LAGS is also studied as well as the device hysteresis width