A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm/sup 2/ die size and a 0.044-/spl mu/m/sup 2/ effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-V/sub CC/ in order to avoid program disturbance issues.     

Variability-insensitive scheme for NAND flash memory interfaces

A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability     

Circuit techniques for 1.5-V power supply flash memory

We describe circuit techniques for a Flash memory which operates with a V_DD of 1.5 V. For the interface between the peripheral circuits and the memory core circuits, two types of level shifter circuits are proposed which convert a V_DD level signal into the high voltage signals needed for high performance. In order to improve the read performance at a low V_DD, a new self-bias bitline voltage sensing scheme is described. This circuit greatly reduces the delay's dependence on bitline capacitance and achieves 19 ns reduction of the sense delay at low voltages. Multilevel storage sensing with this circuit is also discussed     

适于空间图像闪存阵列的非与闪存控制器

提出一种适于空间应用的非与(NAND,not and)闪存控制器。首先,分析了空间相机存储图像的要求,说明了闪存控制器结构的特点。接着,分析了闪存数据存储差错的机理,针对闪存结构组织特点提出了一种基于BCH(Bose-Chaudhuri-Hocquenghem,2108,2048,5)码的闪存纠错算法。然后,对传统BCH编码器进行了改进,提出了一种8bit并行蝶形阵列处理机制。最后,使用地面检测设备对闪存控制器进行了试验验证。结果表明,闪存控制器能快速稳定、可靠地工作,在闪存单页2Kbt/page下可以纠正40bit错误,在相机正常工作行频为2.5kHz下拍摄图像时4级流水线闪存连续写入速度达到133Mbit/s,可以满足空间相机图像存储系统的应用。     

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitlinedirect sensing scheme

A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-μm triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 μm² , the smallest yet reported for 0.25-μm CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized     

NAND flash memory technology utilizing fringing electric field

In this review article, basic properties of NAND flash memory cell strings which consist of cells with virtual source/drain (S/D) (or without S/D) were discussed. The virtual S/D concept has advantages of better scalability, less cell fluctuation due to effectively longer channel length at the same technology node, and less program disturbance. The fringing electric field from the control-gate and/or the floating-gate is essential to induce the virtual S/D (charges) in the space region of the body between control-gates and becomes effective as cell size shrinks. A cell string consisting of planar channel silicon-oxide-nitride-oxide-silicon (SONOS) cells formed in bulk Si substrate needs to have a bit-line body doping of ～5 × 10¹⁷ cm^?3 in the channel and a less doping in the space region to keep high bit-line read current. The floating gate (FG) flash memory cell string gives larger bit-line current compared to that of SONOS flash memory cell string at given similar body doping. Non-planar channel cells like arch and fin-type body structures were more effective to focus the fringing electric field on the space region. The virtual S/D concept is also useful in 3-dimensional (3-D) stacked NAND flash memory where thin film (or nanowire, nanotube) body is adopted.     

A 29-mm2, 1.8-V-only, 16-Mb DINOR flash memory withgate-protected-poly-diode (GPPD) charge pump

A 29-mm², 16-Mb divided bitline NOR (DINOR) flash memory is fabricated using 0.25-μm triple-well three-layer-metal CMOS technology. Read access time is 72 ns at 1.8 V. A poly diode charge-pump technique improves pump efficiency and eliminates the body effect problem     

A new erase method for scaled NAND flash memory device

A suitable bird-beak thickness is crucial to the cell reliability. However, the process control for bird-beak thickness in the edge region is very difficult. A new erase method is proposed in this work to modulate the electron tunneling region of 40 nm floating gate NAND flash memory device. The erasing electron can move to gate center from gate edge under back bias at 0.3 V/− 0.8 V. The Fowler-Nordheim (FN) current of erase operation distributes on the whole channel region, not located at the gate edge region. Results show that the proposed method can improve cell reliability about 33%. TCAD analysis is employed to explain and prove the mechanism. This new erase method is promising for scaled NAND flash memory.     

A 5-V-only 16-Mb flash memory with sector erase mode

A 5-V-only 16-Mb CMOS flash memory with sector erase mode is described. An optimized memory cell with diffusion self-aligned drain structure and channel erase are keys to achieving 5-V-only operation. By adopting this erase method and row decoders to apply negative bias, 512-word sector erase can be realized. The auto chip erase time of 4 s has been achieved by adopting 64-b simultaneous operation and improved erase sequence. The cell size is 1.7 μm×2.0 μm and the chip size is 6.3 mm×18.5 mm using 0.6-μm double-layer metal triple-well CMOS technology     

Circuit techniques for a VLSI memory

This paper describes circuit techniques necessary for dynamic RAMs with high-packing density to implement submicron device technology. An on-chip error checking and correcting technique using bidirectional parity checking is proposed to reduce the soft error rate. In a sense-refresh amplifier, capacitor-coupled presenting is introduced to compensate for threshold imbalance. An on-chip supply voltage conversion is described as a solution for a hot carrier-injection problem. A 256K CMOS dynamic RAM has been designed and fabricated as a test vehicle for these techniques.     

Probability-based static wear-leveling algorithm for block and hybrid-mapping NAND flash memory

Owing to its desirable characteristics, flash memory has become attractive to different hardware vendors as a primary choice for data storage. However, because of a limited number of block-erase lifecycles, it has become mandatory to redesign the existing approaches to maximize the flash memory lifetime. Wear-leveling is a mechanism that helps to evenly distribute erase operations to all blocks and enhance lifetime. This research proposes probability-based static wear-leveling. Based on the Markov Chain theory, the future state depends on the present state. Mapping is implemented according to the present visit probability of each logical block in the next state. In each state, the wear-leveling distribution is computed using the standard deviation to determine whether it exceeds the threshold. If it does exceed the threshold, wear-leveling is maintained throughout all blocks in the flash memory by swapping the hot blocks with cold blocks. Using real system-based traces, we have proved that our proposal outperforms the existing design in terms of wear-leveling.     

基于QC-LDPC码的空间CCD图像NAND闪存存储纠错

为了提高空间CCD相机图像NAND闪存存储可靠性,提出一种基于QC-LDPC码的NAND闪存纠错算法。首先,分析了NAND闪存纠错信道模型;然后,根据闪存特点提出了一种基于QC-LPDC(1056,1024)码的NAND闪存纠错算法,为了加快编码效率提出了校验矩阵构造和高效编码方法,设计的校验阵均是0和1,只有移位和加法运算,非常适合硬件实现;最后,使用地面检测设备对闪存纠错算法进行了试验验证。结果表明,闪存纠错算法能快速稳定、可靠地工作,计算复杂度比较低,算法复杂度仅具为O(N);算法纠错能力高,误码比(BER)为10-6时,本文算法比RS码多0.47dB编码增益;使用65nm CMOS单元库,系统工作频率为250MHz时解码器数据吞吐率达到7.2Gbps;低误码平层,在误比特率为10-8时未出现误码平层。本文的NAND闪存纠错算法满足了空间相机图像存储系统的应用。     

Effects of floating-gate interference on NAND flash memory celloperation

Introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V _T shift of a cell proportional to the V_T change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-μm design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors     

发展3D NAND闪存的意义

首届IC咖啡国际智慧科技产业峰会于2017年1月14日在上海召开,长江存储集团公司CEO杨士宁介绍了对存储器市场的看法,及选择3D NAND闪存作为主打产品的战略思考.     

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.     

Virtual-ground sensing techniques for a 49-ns/200-MHz access time 1.8-V 256-Mb 2-bit-per-cell flash memory

Fast and accurate read operation in 1.8-V 2-bit-per-cell virtual-ground flash memories requires techniques to substantially reduce the read margin loss due to the side-leakage current and the complementary-bit disturbance. The read margin loss caused by the combination effect of these two disturbance mechanisms is serious enough to eliminate the read margin window, which is already small when the power supply voltage is about 1.8 V and when a memory cell stores 2 bits. This paper introduces for the first time the sense current recovery technique to counteract the side-leakage current effect and the differential feedback cascoded bitline control technique to minimize the complementary-bit disturbance. A 1.8-V 256-Mb 2-bit-per-cell virtual-ground flash memory employing the two techniques has been integrated using 0.13-/spl mu/m CMOS technology. These two sensing techniques are essential for the memory to achieve 49-ns initial read access and 200-MHz internal burst read access. The die size is 52 mm/sup 2/ and the cell size is 0.121 /spl mu/m/sup 2/.     

Design methodology of a robust ESD protection circuit for STIprocess 256 Mb NAND flash memory

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n^- junction with n⁺ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness     

一种基于NAND闪存高效的页面替换算法

针对不同NAND闪存读写操作成本比例的不同,提出一种具有高效页面替换功能的EPRA算法。在内存中,每个受害者候选页被分成固定数量的闪存页面。EPRA给每个受害者候选页分配权重值,在选择与修改页面时对权重进行调节,从候选页中选择具有最小权重值的页面作为受害者页。EPRA算法把受害者页中分为热的闪存页和冷的闪存页,并把这些数据写到NAND闪存中不同空闲的块中。仿真实验结果表明,EPRA算法使用在不同种类的NAND闪存中时,性能优于现有的页面替换算法。     

A quick intelligent page-programming architecture and a shieldedbitline sensing method for 3 V-only NAND flash memory

This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure. A 3 V-only experimental NAND flash memory, developed in a 0.7-μm NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-μs random access time with a 2.7-V power supply. The page-programming is completed after the 40-μs program and 2.8-μs verify read cycle is iterated 4 times. The block-erasing time is 10 ms     

Data retention characteristics of sub-100 nm NAND flash memory cells

In contrast to the conventional theories, we have revealed that the most distinguished mechanism in the data retention phenomenon after Fowler-Nordheim (FN) stress in sub-100 nm NAND Flash memory cells is the annihilation of interface states. Interface state generation rate increases rapidly as the channel width of NAND flash cell decreases. Comparison of interface states and stress-induced leakage current (SILC) component during retention mode shows that the annihilation of interface states strongly affects data retention characteristics of the programmed cells.