共查询到20条相似文献,搜索用时 31 毫秒
1.
《Microelectronics Journal》2007,38(6-7):783-786
For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO2-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node. 相似文献
2.
A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO2/HfO2 dielectrics (effective oxide thickness is less than 1 nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper. 相似文献
3.
Roberto Grassi Stefano Poli Susanna Reggiani Elena Gnani Antonio Gnudi Giorgio Baccarani 《Solid-state electronics》2008,52(9):1329-1335
The impact of acoustic and optical phonon scattering on the performance of CNT-FETs is investigated using a full-quantum transport model within the NEGF formalism. Different gate lengths, dielectric materials and chiralities are considered. It is shown that the use of a high-κ dielectric lowers the off-current dominated by phonon-assisted band-to-band tunneling. The device scalability is demonstrated: with the oxide thickness fixed to 1.5 nm, good performance is obtained with 15 nm and 10 nm gate lengths with SiO2 and HfO2 gate dielectrics, respectively. The role of phonon scattering in CNT-FETs of different chiralities is investigated for the HfO2 devices. A similar analysis has also been carried out for source/drain underlap geometries. The results confirm that the calculation of the off-currents and delay times is strongly influenced by phonon scattering. 相似文献
4.
Martin M. Frank SangBum Kim Stephen L. Brown John Bruley Matthew Copel Marco Hopstaken Michael Chudzik Vijay Narayanan 《Microelectronic Engineering》2009,86(7-9):1603-1608
We discuss options for metal–oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity (‘high-k’) gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO2 can be scaled to capacitance equivalent thickness in inversion (Tinv) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si3N4 and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based ‘higher-k’ dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO2 as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO2 at the poly-Si contact. We further address the performance of Si3N4 and HfO2 as oxygen barrier layers. 相似文献
5.
T. Yu C.G. Jin Y.J. Dong D. Cao L.J. Zhuge X.M. Wu 《Materials Science in Semiconductor Processing》2013,16(5):1321-1327
We investigated the temperature dependence of C–V and I–V characteristics in p-type Metal Oxide Semiconductor (MOS) capacitors with HfO2/SiO2 dielectric stacks. Dramatic degradation in the C–V characteristics at/over the measurement temperature of 125 °C was observed, which was caused by the increased effective oxide thickness, oxide trapped charge density, and interfacial density of state (Dit) with rising temperature during bias temperature stress. In the accumulation region, the leakage current density displayed strong temperature dependence in the ?3 V<Vg<0 V region, as expected for the direct tunneling compared to the trap-assisted component (DT+TAT) effect. The conduction mechanism was transformed into Fowler–Nordheim (FN) tunneling (weak T and Vg dependence) from DT+TAT (strong T and Vg dependence) at Vg <?3 V, which was confirmed by FN tunneling fitting. According to the conventional Shockley–Read–Hall model, the different levels in Dit were found at various measurement temperatures to interpret the strong temperature dependence and weak Vg dependence inversion current property. 相似文献
6.
S.F. Wan Muhamad Hatta N. Soin D. Abd Hadi J.F. Zhang 《Microelectronics Reliability》2010,50(9-11):1283-1289
Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advanced-process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engineering and laser annealing in order to achieve high on-state drain current drive performance. To explore NBTI effects on an advanced-process sub-micron device, the 45 nm high-k PMOS transistor was simulated extensively with a wide range of geometric and process variations. The device was simulated at varying thicknesses in the dielectric layer, oxide interfacial layer, metal gate and polysilicon layer. In order to observe the NBTI effect on process variation, the NBTI degradation of the 45 nm advanced-process PMOS is compared with a 45 nm PMOS device which does not employ process-induced stress and incorporates the conventional rapid thermal annealing (RTA) as compared to the laser annealing process which is integrated in the advanced-process device flow. The simulation results show increasing degradation trend in terms of the drain current and threshold voltage shift when the thicknesses of the dielectric layer, oxide layer as well as the metal gate are increased. 相似文献
7.
P.C. Feijoo M. Cho M. Togo E. San Andrés G. Groeseneken 《Microelectronics Reliability》2011,51(9-11):1521-1524
PBTI degradation on FinFETs with HfO2/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation. 相似文献
8.
Piyas Samanta Chin-Lung Cheng Yao-Jen Lee Mansun Chan 《Microelectronic Engineering》2009,86(7-9):1767-1770
We have investigated electrical stress-induced positive charge buildup in a hafnium aluminate (HfAlO)/silicon dioxide (SiO2) dielectric stack (equivalent oxide thickness = 2.63 nm) in metal–oxide–semiconductor (MOS) capacitor structures with negative bias on the TaN gate. Various mechanisms of positive charge generation in the dielectric have been theoretically studied. Although, anode hole injection (AHI) and valence band hole tunneling are energetically favorable in the stress voltage range studied, the measurement results can be best explained by the dispersive proton transport model. 相似文献
9.
We have modeled and characterized scaled Metal–Al2O3–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (KA = 9) blocking insulator of ALD deposited Al2O3 (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 1018 traps/cm3 eV. The devices show excellent endurance with no memory window degradation to 106 write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices. 相似文献
10.
《Solid-state electronics》2006,50(9-10):1667-1669
In this paper, we present a new Polysilicon–Aluminum Oxide–Nitride–Oxide–Silicon (SANOS) device structure suitable for future nonvolatile semiconductor memories. Replacing SiO2 with a high-K material, Al2O3 (Kf = 9) as the top blocking layer of the conventional SONOS device increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer with its dielectric constant during write and erase operations. Therefore, this new device can achieve lower programming voltages and faster programming speed than the conventional SONOS device. We have fabricated SANOS capacitors with 2 nm tunnel oxide, 5 nm silicon nitride and 8 nm aluminum oxide and studied the programming speed and charge retention characteristics of the new devices. These new SANOS devices achieve a 2 V reduction in the programming voltages with 2.1 V initial memory window. 相似文献
11.
Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO2 and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO2/HfSiON with a U-shape nitrogen profile and a like-Si/SiO2 interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO2 and 1.2-nm HfSiON exhibits the lowest gate leakage. 相似文献
12.
Hafnium dioxide deposited by RF sputtering is used as the gate insulator of metal–insulator–silicon–carbide (MISiC) Schottky-diode hydrogen sensors. Sensors with different gate insulator thicknesses are fabricated for investigation. Their hydrogen-sensing properties are compared with each other by taking measurements at various temperatures and hydrogen concentrations using a computer-controlled measurement system. Experimental results show that for the same insulator thickness, the HfO2 sensor is more sensitive than its SiO2 counterpart. This should be mainly attributed to the larger barrier-height at the Pt/HfO2 interface which can reduce the current of the sensor before hydrogen exposure. Moreover, the sensitivity initially increases with the thickness of the HfO2 film because a thicker oxide layer can provide a larger barrier-height reduction upon hydrogen exposure. However, further increasing the thickness of the HfO2 dielectric beyond about 3.3 nm reduces the sensitivity, possibly due to more trapped charges in thicker high-k dielectric which can screen the effect of the polarized hydrogen layer. 相似文献
13.
Emilie Bernard T. Ernst B. Guillaumot N. Vulliet X. Garros V. Maffini-Alvaro P. Coronel T. Skotnicki S. Deleonibus 《Solid-state electronics》2008,52(9):1297-1302
In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO2, TiN/SiO2 or N+ poly-Si/SiO2 are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO2 gate stack demonstrates the best ION/IOFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V. 相似文献
14.
Youhei Sugimoto Hideto Adachi Keisuke Yamamoto Dong Wang Hideharu Nakashima Hiroshi Nakashima 《Materials Science in Semiconductor Processing》2006,9(6):1031
High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO2/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfOx and SiO2. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfOx/SiO2/Si to HfSixOy/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO2. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO2. 相似文献
15.
K. Čičo D. Gregušová J. Kuzmík M. Jurkovič A. Alexewicz M.-A. di Forte Poisson D. Pogany G. Strasser S. Delage K. Fröhlich 《Solid-state electronics》2012,67(1):74-78
We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al2O3 gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al2O3 growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ~0.6 A/mm (VGS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al2O3 dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing. 相似文献
16.
K. O. Petrosyants D. A. Popov L. M. Sambursky I. A. Kharitonov 《Russian Microelectronics》2016,45(7):460-463
The models of electrophysical effects builtinto Sentaurus TCAD have been tested. The models providing an adequate modeling of deep submicron high-k MOSFETs have been selected. The gate and drain leakage currents for 45 nm MOSFETs with polysilicon gate and SiO2, SiO2/HfO2 and HfO2 gate dielectrics have been calculated using TCAD. It has been shown that the replacement of the traditional SiO2 gate oxide by an equivalent HfO2 dielectric reduces the gate leakage current by several orders of magnitude due to the elimination of the impact of the tunneling effect. Besides, the threshold voltage, saturation drain current, mobility, transconductance, etc., degrade within a range of 10–20%. 相似文献
17.
Changhwan Choi Takashi Ando Eduard Cartier Martin M. Frank Ryosuke Iijima Vijay Narayanan 《Microelectronic Engineering》2009,86(7-9):1737-1739
We present a novel metal gate/high-k complementary metal–oxide–semiconductor (CMOS) integration scheme with symmetric and low threshold voltage (Vth) for both n-channel (nMOSFET) and p-channel (pMOSFET) metal–oxide–semiconductor field-effect transistors. The workfunction of pMOSFET is modulated by oxygen in-diffusion (‘oxygenation’) through the titanium nitride metal gate without equivalent oxide thickness (EOT) degradation. A significant Vth improvement by 420 mV and an aggressively scaled capacitance equivalent thickness under channel inversion (Tinv) of 1.3 nm is achieved for the pFET by using a replacement process in conjunction with optimized oxygenation process. Immunity of nMOSFET against oxygenation process is demonstrated. 相似文献
18.
R. Kakoschke L. Pescini J.R. Power K. van der Zanden E.-O. Andersen Y. Gong R. Allinger 《Solid-state electronics》2008,52(4):550-556
We have successfully integrated 2 Mb arrays with SiO2/Al2O3 stacks as inter-poly dielectric (IPD) fabricated in a proven 130 nm embedded Flash technology. Gate stack write/erase high voltages (HV) can be reduced by 3 V. Write/erase distributions show evidence of bit pinning which can be explained by barrier lowering along Al2O3 grain boundaries. Reliability assessment of the 2 Mb array reveals promising data retention and cycle endurance, indicating the absence of charge trapping in the high-k IPD. Despite several integration issues, these results demonstrate the high potential of Al2O3 IPDs in embedded Flash technologies. 相似文献
19.
《Microelectronic Engineering》2007,84(9-10):2138-2141
Enhancement mode, high electron mobility MOSFET devices have been fabricated using an oxide high-κ gate dielectric stack developed using molecular beam epitaxy. A template layer of Ga2O3, initially deposited on the surface of the III-V device unpins the GaAs Fermi level while a (GdxGa1−x)2O3 bulk ternary layer forms the highly resistive layer to reduce leakage current through the dielectric stack. A midgap interface state density of ∼2 × 1011 cm−2 eV−1 and a dielectric constant of 20 are determined using electrical measurements.. N-channel MOSFETs with a gate length of 1 μm and a source-drain spacing of 3 μm show a threshold voltage, saturation current and transconductance of 0.11 V, 380 mA/mm and 250 mS/mm, respectively. 相似文献
20.
Metal-Oxide-Silicon (MOS) structures containing silicon nanoparticles (SiNPs) in three different gate dielectrics, single SiOx layer (c-Si/SiNPs-SiOx), two-region (c-Si/thermal SiOx/SiNPs-SiOx) or three-region (c-Si/thermal SiO2/SiNPs-SiOx/SiO2) oxides, were prepared on n-type (100) c-Si wafers. The silicon nanoparticles were grown by a high temperature furnace annealing of sub-stoichiometric SiOx films (x=1.15) prepared by thermal vacuum evaporation technique. Annealing in N2 at 700 or 1000 °C leads to formation of amorphous or crystalline SiNPs in a SiOx amorphous matrix with x=1.8 or 2.0, respectively. The three-region gate dielectric (thermal SiO2/SiNPs-SiO2/SiO2) was prepared by a two-step annealing of c-Si/thermal SiO2/SiOx structures at 1000 °C . The first annealing step was carried out in an oxidizing atmosphere while the second one was performed in N2. Cross-sectional Transmission Electron Microscopy and X-ray Photoelectron Spectroscopy have proven both the nanoparticle growth and the formation of a three region gate dielectric. Annealed MOS structures with semitransparent aluminum top electrodes were characterized electrically by current/capacitance–voltage measurements in dark and under light illumination. A strong variation of the current at negative gate voltages on the light intensity has been observed in the control and annealed at 700 °C c-Si/SiNPs-SiOx/Al structures. The obtained results indicate that MOS structures with SiO1.15 gate dielectric have potential for application in light sensors in the NIR–Visible Light–UV range. 相似文献