Fabrication of horizontal current bipolar transistor (HCBT)

The fabrication and characterization of very compact horizontal current bipolar transistor (HCBT) is presented. The active transistor region is processed in the sidewalls of the n-hill, which makes this structure attractive for the integration with pillar-like CMOS with minimum process additions. HCBT technology is simple with 5 lithography masks. The active n-hills are isolated by newly developed chemical-mechanical planarization (CMP) and etch back of oxide. The <110> substrate is used for HCBT fabrication utilizing <111> crystal planes as the active sidewalls. This enables the use of crystallographic dependent etchants for the minimization of the sidewall roughness and dry etching defects, as well as increases the controllability and repeatability of intrinsic transistor doping process. The active transistor regions are processed by angled ion implantation in self-aligned manner. The processed structures result in a cutoff frequency-breakdown voltage (f/sub T/BV/sub CEO/) product of 69.5 GHzV and current gain-Early voltage (/spl beta/V/sub A/) of 4800 V. The high-frequency characteristics are limited by the wide extrinsic base due to the coarse lithography resolution used for fabrication. It is shown by simulations that the improvement of (f/sub T/) and maximum oscillation frequency (f/sub max/) up to 24 and 50 GHz, respectively, can be achieved with finer lithography employed.     

Horizontal current bipolar transistor (HCBT) process variations for future RF BiCMOS applications

Two different process designs of horizontal current bipolar transistor (HCBT) technology suitable for future RF BiCMOS circuits are presented. The active transistor region is built in the defect-free sidewall of 900-nm-wide n-hills on a [110] wafer. The collector n-hill region is partially etched at the extrinsic base-collector periphery, whereas the extrinsic base is self-protected, resulting in reduced collector-base capacitance (C/sub BC/) and minimized volume of the extrinsic regions. The effect of doping levels at different regions on the transistor performance is examined in the two process designs. The fabricated HCBTs exhibit cutoff frequencies (f/sub T/) from 19.2 to 25.6 GHz, maximum frequencies of oscillations (f/sub max/) from 32.2 to 39.6 GHz, and collector-emitter breakdown voltages (BV/sub CEO/) between 4 and 5.2 V, which are the highest f/sub T/ and the highest f/sub T//spl middot/BV/sub CEO/ product compared to existing silicon-on-insulator (SOI) lateral bipolar transistors (LBTs). The compact nature of the HCBT structure and low-cost technology make it suitable for integration with advanced pillar-like CMOS and SOI CMOS devices.     

Horizontal current bipolar transistor (HCBT): a new concept ofsilicon bipolar transistor technology

A new concept of silicon bipolar transistor technology is proposed. The resulting horizontal current bipolar transistor (HCBT) is simulated assuming the 0.25 μm technology. The surface of the device is smaller than conventional super-self aligned bipolar transistors. The same doping profile as in known vertical current devices is achieved by simpler technology using single polysilicon layer, without conventional epitaxial and n⁺ buried layers and with reduced number of lithography masks and technological steps. The simulated dc and ac characteristics of HCBT are similar to the characteristics of standard SST devices     

CMOS-compatible lateral bipolar transistor for BiCMOS technology.II. Experimental results

For Pt.I see ibid., vol.39, no.4, p.948-51 (1992). Characteristics of a CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs are described. The proposed transistor has a structure analogous to that of the NMOS transistor, which employs a source and drain self-aligned structure to form an emitter and collector. The obtained values of h_FE, BV_CEO, R _CS, f_Tmax, and r_bb', are 20, 7 V, 50 Ω, 6.3 GHz, and 450 Ω, respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 and 0.53 ns when load capacitances are 1 and 2 pF, respectively. These values are comparable to those for BiCMOS circuits using the conventional vertical bipolar transistors     

A low-cost fully self-aligned SiGe BiCMOS technology using selective epitaxy and a lateral quasi-single-poly integration concept

We present a low-cost concept for a self-aligned SiGe heterojunction bipolar transistor (HBT). In conventional double-poly HBTs, the base link is formed by use of a sacrificial layer to grow the SiGe epitaxy between an external base polysilicon and the silicon substrate, resulting in a vertical base link. In this concept, the SiGe epitaxy is laterally connected to the extrinsic base poly forming a short and fully self-aligned base link. While strongly reducing process complexity, this concept maintains a minimal link resistance between the internal and the external base. We demonstrate the integration of this HBT with balanced dc and ac performance in a 0.25-/spl mu/m bipolar complementary metal-oxide-semiconductor technology, featuring all passive devices necessary for RF design. The bipolar multitransistor yield shows similar values compared to our conventional double-poly integration concept.     

A BiCMOS technology with 660-MHz vertical p-n-p transistor foranalog/digital ASICs

A fully complementary BiCMOS technology based on a 2-μm process designed for 12-V analog/digital applications is described. In this technology, a triple diffused vertical p-n-p transistor and n-p-n bipolar and CMOS devices are integrated in a single chip. A transition frequency of 660 MHz and a collector-to-emitter breakdown voltage of over 15 V have been obtained for the collector-isolated p-n-p transistor by adding only one extra mask to a conventional 2-μm BiCMOS process. The total number of masks is 20 with double-layer metallization. A unity gain frequency of 52 MHz and a DC gain of 85 dB have been obtained for a single-supply operational amplifier with a vertical p-n-p first stage. The propagation delay time for a CMOS two-NAND gate was 1.27 ns driving three loads and 3 mm of metal     

T-emitter bipolar power transistor with negative-temperature-gradient current gain

A PNP epitaxial-base power transistor with double diffused emitter (T-emitter) which exhibits a negative temperature gradient for ? is described. Qualitative analysis shows that a fall-off in ? with increase in temperature is a consequence of both the T-emitter geometry and the boron double diffused emitter area. Measurements on realised transistors give a mean value of d?/dt of ?0.25 at temperatures ranging from 20°C to 110°C.     

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.     

Profiled current drive for pulsed bipolar transistor switching

Preliminary investigations have been made of the profiling of base current drive to obtain fast turn-on without lifetime pulse stretching and turn-off delays.<>     

A stripe-geometry InGaAsP/InP heterojunction bipolar transistor suitable for optical integration

A stripe-geometry InGaAsP/InP heterojunction bipolar transistor (HBT) was fabricated for the first time. High current gain (β > 500) and high collector current (Ic> 200 mA) were obtained in devices with an emitter-down configuration. The HBT was successfully integrated with a double-heterostructure (DH) laser, resulting in the first realization of laser operation in a vertical integration.     

A very small bipolar transistor technology with sidewall polycidebase electrode for ECL-CMOS LSIs

Very small, high-performance, silicon bipolar transistors (SPOTEC) are developed for use in ECL-CMOS LSIs. The transistors are fabricated with a sidewall polycide base; chemical vapor deposition is used to selectively deposit tungsten on the sidewall surface of the polysilicon base. The tungsten is then silicided. This self-aligned polycide technology makes a narrow (0.4-μm wide), low-resistance (7 Ω/□) base electrode possible. Narrow U-groove isolation and narrow collector metallization techniques are used to reduce the transistor area to 10 μm². A shallow E-B junction and base layer have now been formed by using rapid-vapor-phase doping. The resulting transistors have good I-V characteristics without leakage current or high current gain. They have a high cut-off frequency of 37 GHz (53 GHz with pedestal collector ion implantation and thin epitaxial layer) and small junction capacitances. These transistors facilitate the development of very-high-speed, high-density ULSIs     

Lateral PNP GaAs bipolar transistor with minimized substrate current

Lateral pnp bipolar transistors have been fabricated using Be implantation to define the emitter and collector areas. The base area (1 - 2 µm wide) has been protected against Be ions during implantation by SiO2and photoresist. The lateral straggling and diffusion during the anneling process reduces the base width, which can be adjusted with the annealing temperature and time. Between the active n-GaAs layer and substrate, a n-Ga0.7Al0.3As layer is deposited. The Be ions penetrating the GaAs/GaAlAs interface form a pn junction in the GaAlAs layer below the emitter and collector area. This reduces the current by several orders of magnitude through the parasitic emitter-substrate (base) diode compared to a GaAs pn junction, due to the higher band gap. For these devices with an effective base width of 0.5 µm, a current gain of 10 in common emitter configuration has been obtained.     

Quarter micron BiCMOS technology platform with implanted-base- or SiGe-bipolar transistor for wireless communication ICs

We present a modular 0.25 μm ASIC-compatible, double-poly self-aligned BiCMOS technology comprising either an implanted-base 45 GHz bipolar transistor or a 80 GHz-HBT with selective SiGe-epitaxy. All passive devices for RF-design are integrated, including a 7 fF/μm² stacked MIS-/MIM-capacitor.     

Self-aligned SiGe-base heterojunction bipolar transistor byselective epitaxy emitter window (SEEW) technology

In the device a SiGe epitaxial base is integrated in a structure which uses in situ doped epitaxial lateral overgrowth for the formation of the emitter window and the extrinsic base contact. Nearly ideal I -V characteristics have been achieved for a base width of 60 nm with an intrinsic base resistance of 4.6 kΩ/□ and for emitter widths down to 0.4 μm. A DC collector current enhancement factor of 3.1 was obtained relative to a Si homojunction transistor with a 1.25 times higher intrinsic base resistance. The breakdown voltage BV_CBO is identical for both Si and SiGe devices, even though the collector-base depletion region is partly overlapped with the reduced-bandgap SiGe strained layer. The lower BV_CEO, measured for the SiGe-base transistor, is due to the higher current gain. Based on these results the fabrication of high-speed bipolar circuits that take advantage of SiGe-base bandgap engineering seems possible using selective epitaxy emitter window (SEEW) technology     

A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications

A CMOS-compatible gate-controlled lateral BJT (GC-LBJT) was prepared with a conventional 90 nm CMOS technology for radio frequency system-on-chip (RF SoC) applications. The emitter injection efficiency and the doping profile in P-well were optimized by properly controlling source, drain, and well implants. Consequently, the GC-LBJT with a gate length of 0.15 μm can achieve a current gain over 2000 and 17/19 GHz for the f_T/f_max, respectively, which are 1000%, 200%, and 60% improvements in current gain, f_T and f_max, respectively as compared to the LBJT reported previously.     

An NMOS input merged bipolar/sidewall-MOS transistor with a bypasssidewall MOS transistor (NBiBMOS transistor)

The concept of merging a vertical n-p-n bipolar and two sidewall NMOS transistors into an NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS transistors, is significant even when the output voltage (V_CE or V_DE) is less than the turn-on voltage of the n-p-n bipolar transistor (V_BE=~0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and DC characterizing the NBiBMOS transistor structures, which occupy ~1.2 times the area of a single n-p-n bipolar transistor. The NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor, because the body-source junction of the bypass NMOS transistor is forward biased     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

An improved heterostructure-emitter bipolar transistor (HEBT)

An N-Al_0.5Ga_0.5As/n-GaAs heterostructure-emitter bipolar transistor (HEBT), grown by MBE, has been fabricated with improved performance. The Al_0.5Ga_0.5As layer with higher valence-band offset ΔE_v offers better confinement of minority carriers (holes). A small offset voltage of about 80 mV and a high common-emitter current gain of 180 were measured for large-area devices. On the other hand, the adequate design of an n-GaAs emitter layer also plays an important role in device performance. The strongly knee-shaped characteristics and reachthrough effect were observed in those devices fabricated with 12 a thin n-GaAs emitter layer     

GaAs inversion-base bipolar transistor (GaAs IBT)

A completely new type of GaAs bipolar transistor with a base formed by a two-dimensional hole gas has been fabricated. The transistor has no metallurgical base layer but has an extremely thin inversion hole layer working as a base layer. The current gain β = 5.6 at 77 K and β = 17.1 at 300 K was obtained for the common emitter mode.     

A novel trench clustered insulated gate bipolar transistor (TCIGBT)

A new trench clustered insulated gate bipolar transistor (TCIGBT) is reported. In this device, a multitude of UMOS cathode cells is enclosed within a common n-well and p-well. The TCIGBT provides a unique self-clamping feature to protect the trenches from high electric fields. The simulation results based on 1.2 kV nonpunchthrough technology indicate an improvement of 25% in on state and 28% in the turn-off losses in comparison to the state-of-the-art trench IGBT. The saturation current levels of the TCIGBT, which can be designed independent of the forward drop, are also lower.