共查询到19条相似文献,搜索用时 78 毫秒
1.
设计了一种新型叉状电磁带隙结构(简称EBG)。该型EBG结构与传统的蘑菇状EBG结构相比尺寸减小近40%。在不改变周期的情况下,通过调整伸长窄带长度可以改变带隙特性频率。测量结果显示,新型EBG结构在宽频带内具有良好的阻带特性。用在微波集成电路中,可以减小电路尺寸和抑制阻带内波纹。 相似文献
2.
针对一般谐振型电磁带隙结构相对带宽比较窄的特点,依据电磁带隙结构带隙形成机理和等效电路分析模型,该文提出了一种基于低介电常数低成本基底的紧凑宽带平面电磁带隙结构。实验结果表明,新结构具有54.1%的相对带宽,相比文献结构有超过100%的相对带宽改善,并且中心频率降低了25.2%,达到了实现紧凑宽带UC-EBG结构的目的。 相似文献
3.
该文研究了实现宽带EBG(Electromagnetic Band-Gap)结构的方法。仿真结果表明利用周期渐变技术可以明显增加阻带带宽,进而采用单元尺寸加窗技术可以改善通带和阻带的平坦度。在该文的例子中,-20dB的阻带带宽增加了2096以上,3GHz以下的通带插损小于0.4dB。制作了相应的实际电路,实验结果与仿真结果基本相符。 相似文献
4.
根据不同周期平面电磁带隙(EBG)结构所具有的不同带隙特性以及平面EBG结构的等效电路,提出一种新型多周期平面EBG结构。通过Ansoft HFSS软件对该EBG结构的电磁带隙特性进行仿真验证。结果表明:所提出的EBG结构抑制深度为-30dB时,阻带范围为0.7~8.4GHz,阻带宽度为7.7GHz.相对于传统大周期和小周期平面EBG结构,其阻带宽度分别增加2.1GHz和1.2GHz.仿真结果也表明新型EBG结构可以有效抑制同步开关噪声(SSN),并为展宽平面EBG结构的禁带带宽提供一种新方法。最后,通过时域仿真验证新结构具有较好的信号完整性。 相似文献
5.
本文通过对电磁带隙(EBG)结构等效电路的分析,研究了展宽其带隙带宽的方法,提出了一种新型的实现方法——组合单元法.以金属贴片表面螺旋电感的EBG结构为冽,验证了该方法的有效性和正确性,为解决EBG结构存在的带隙带宽较窄的问题提供了一种新的思路。 相似文献
6.
该文运用HFSS和S参数模型,分别从时域和频域的角度通过仿真实验研究和分析了电磁带隙(EBG)结构对信号传输特性的影响,研究表明EBG结构的周期性高阻平面导致了传输信号的反射与滤波,严重影响了信号传输质量。平面周期越小,影响越大。最后通过实验仿真和理论分析给出了EBG结构的应用规则。 相似文献
7.
电磁带隙结构是光子晶体中的一种,它可以广泛地应用于微波、毫米波波段.研究了一种具有蝶形单元的电磁带隙结构,通过理论分析获得它的ABCD矩阵,将ABCD矩阵转换为散射矩阵,进而得到该结构的频率特性.在这种电磁带隙结构中引入缺陷,采用同样的分析方法获得它的频率特性.通过仿真计算可以看出,具有蝶形单元的电磁带隙结构大约有2.8 GHz带宽的阻带,相对带宽为52%;而具有缺陷的电磁带隙结构在阻带中形成一个具有一定带宽的通带,且通带的频率很容易调整. 相似文献
8.
针对工程应用的要求,根据Mushrooa-like EBG结构的局域谐振原理和等效电路分析模型,提出了一种双带隙紧凑电磁带隙结构.该结构通过引入交织螺旋导带来增加等效电感效应,减小了周期单元尺寸.采用了交替排列凹凸金属贴片,实现了可重构的双频率带隙.最后通过对3×5 EBG单元阵列的仿真实验,证明了该设计是有效的. 相似文献
9.
提出了一种双层电磁带隙(Electromagnetic Band Gap,EBG)结构,构建其电感电容(Inductance Capacitance,LC)等效电路并推算出双层EBG的谐振表达式,通过仿真软件对双层EBG结构上下两层的参数进行调节,分析各参数对电磁特性的影响规律,结果表明双层EBG可以产生两个零位相频率点,下层结构对应的零位相频率主要与下层的介质厚度及贴片大小有关,几乎不受上层的影响,而上层结构的谐振频率不仅与其自身参数有关也要考虑下层对其的影响,仿真结果与理论分析一致.该结构为EBG的具体设计和应用提供了指导依据. 相似文献
10.
应用悬置微带线方法(SMM)对二维EBG结构进行了测量和计算。对二维电小EBG(UC—EBG和PV—EBG)的特性用SMM法进行了统一的实验和仿真分析。与其他方法对比,由于采用了“强耦合”结构,更能显现出二维电磁带隙结构的特性。同时提出了新型的悬置微带贴片的EBG天线,该天线结构紧凑,更利于EBG的实际应用。 相似文献
11.
Journal of Communications Technology and Electronics - A Compact U-shaped multiple-inputs and multiple-output (MIMO)-antenna with dimensions of 23 × 47 mm2 has been proposed for... 相似文献
12.
Two kinds of compact electromagnetic band gap (EBG) structures are designed. A two layer compact EBG structure configured with cross spiral shape line inductors and interdigital capacitors is first presented. Because of its significantly enlarged equivalent inductor and capacitance, the period of the lattice is approximately 4.5% of the free space wavelength. By insetting several narrow slits in the ground plane, the bandwidth of the main bandgap is enhanced by nearly 19%. Further effort has been made for designing a three layer compact EBG structure. Simulation results show that its period is reduced by about 26% compared to that of proposed two layer EBG structure, and the bandwidth of the main bandgap is about 3 times as that of the proposed two layer EBG structure. The detailed designs including a two layer compact 3×7 EBG array with and without defect ground plane and the three layer EBG array are given and simulation results are presented. 相似文献
13.
In this paper, a novel compact semi-circular slot (SCS) 2 × 2 MIMO antenna is presented for 5G NR sub-6 GHz applications with high isolation. The proposed antenna consists of a semi-circular slot in ground plane, U-shaped stub, and 50-ohm microstrip feed line. The novelty of this paper are the Semi-Circular Slot acts a radiator, the port isolation is enhanced using a simple conductor strip as a neutralization line, very compact in size, low ECC, and good impedance matching. The overall size of the proposed SCS MIMO antenna is 16 mm x 21 mm, and FR4 substrate is used with thickness of 1.6 mm. The two SCS antenna elements are separated by edge-to-edge distance of 1mm (\(=0.019\lambda _{0}\)). The proposed compact MIMO antenna design is simulated using Ansys HFSS. To validate SCS MIMO antenna, a prototype was fabricated and tested. The measured results are attained at 5.5 GHz with isolation greater than 25dB, impedance bandwidth (S11\(<-10\) dB) covers from 5.10 GHz to 5.80 GHz with return loss of ? 39.5 dB. The MIMO antenna parameters, ECC, CCL, TARC, and MEG are studied, and the values are obtained within acceptable limits. The measured and simulated antenna results are almost similar. This compact MIMO antenna is suitable for 5G communications in sub-6 GHz wifi-5 band applications. 相似文献
14.
A waveguide polarizer with resonant notches in a septum is investigated. The Wiener-Hopf techniques employed to derive theoretical design data and the results are compared to experiments for a single-notch and a double-notch design. It is concluded that the agreement is good and the design useful for narrowband applications. 相似文献
15.
文中提出了一种具有准各向同性辐射能力的紧凑平面天线。为了实现良好的准各向同性辐射性能,首先基于理想且相互垂直的电偶极子和磁偶极子辐射源模型进行了理论分析。电小环加载的电偶极子工作于三次模时,长直金属条和电小环分别等效为电偶极子和磁偶极子,存在天然的90°相位差。由于电小环辐射能力弱,所以初始的全空间增益差远大于10 dB。因此,文中通过将长金属条弯折成有切口的长方形,降低电偶极子的辐射能力并提高等效磁偶极子的辐射能力,实现了准各向同性辐射方向图。为了验证设计的有效性,加工并测试了所提出的紧凑天线,其尺寸为0. 28λ0 ×0. 26λ0 ×0. 01λ0,λ0 是中心频率对应的自由空间中的波长。测试结果表明,该紧凑天线具有3. 6%的-10 dB 阻抗带宽和全空间内增益变化小于4. 5 dB 的辐射特性。 相似文献
16.
In this paper, novel compact ultrawideband (UWB) antennas are proposed and successfully demonstrated within the bandwidth with the ratio of the maximum and minimum frequency to be more than 30. The results from electromagnetics (EM) simulation and measurement show good agreement. From the EM simulation results, the electromagnetic wave could be radiated to the free space through the antenna only if the antenna impedance were matched to one of its feed systems within the bandwidth. The developed antenna with a small size of 17 $times$ 17 $times $ 12 mm$^{3}$ shows voltage standing wave ratio (VSWR) of less than 2.5 : 1 from 3 to 100 GHz for the simulated data, and less than 2 : 1 from 3 to 50 GHz for the measured data. The gain of the developed antenna is more than 2 dBi from 3.1 to 10.6 GHz in the application of high-speed wireless digital communication system. 相似文献
17.
本文提出了一种新型的紧凑型人工磁导体(AMC)结构,同样的单元尺寸可以获得较低频率的反射相位阻带带隙,可以比较有效地解决AMC结构的大尺寸问题。制作了相应的实际电路,测量结果与仿真结果基本一致。 相似文献
18.
This brief presents a novel computationally efficient design and implementation of a Rayleigh flat fading-channel simulator. To generate complex Gaussian variates with the required U-shaped power spectrum, the simulator utilizes an infinite-impulse response (IIR) spectrum shaping filter followed by multistage interpolators and low-pass IIR filters. The new simulator significantly simplifies the characterization of wireless systems by providing a fast and area-efficient field-programmable gate array (FPGA) implementation of the fading channel. Our fixed-point Rayleigh fading-channel simulator utilizes only 4% of the configurable slices, 20% of the dedicated multipliers, and 2% of the available memories on a Xilinx Virtex2P XC2VP100-6 FPGA, while generating 25 million fading variates per second. The parameterized fading-channel simulator can be readily reconfigured to accurately simulate a wide variety of different channel characteristics. 相似文献
19.
A compact, fast, and accurate realization of a digital Gaussian variate generator (GVG) based on the Box-Muller algorithm is presented. The proposed GVG has a faster Gaussian sample generation rate and higher tail accuracy with a lower hardware cost than published designs. The GVG design can be readily configured to achieve arbitrary tail accuracy (i.e., with a proposed 16-bit datapath up to plusmn15 times the standard deviation sigma) with only small variations in hardware utilization, and without degrading the output sample rate. Polynomial curve fitting is utilized along with a hybrid (i.e., combination of logarithmic and uniform) segmentation and a scaling scheme to maintain accuracy. A typical instantiation of the proposed GVG occupies only 534 configurable slices, two on-chip block memories, and three dedicated multipliers of the Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) and operates at 248 MHz, generating 496 million Gaussian variates (GVs) per second within a range of plusmn6.66sigma. To accurately achieve a range of plusmn9.4sigma, the GVG uses 852 configurable slices, three block memories, and three on-chip dedicated multipliers of the same FPGA while still operating at 248 MHz, generating 496 million GVs per second. The core area and performance of a GVG implemented in a 90-nm CMOS technology are also given. The statistical characteristics of the GVG are evaluated and confirmed using multiple standard statistical goodness-of-fit tests. 相似文献
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