Characterizing and optimizing TPC-C workloads on large-scale systems using SSD arrays在大规模系统上优化 TPC-C 评测程序

Transaction processing performance council benchmark C (TPC-C) is the de facto standard for evaluating the performance of high-end computers running on-line transaction processing applications. Differing from other standard benchmarks, the transaction processing performance council only defines specifications for the TPC-C benchmark, but does not provide any standard implementation for end-users. Due to the complexity of the TPC-C workload, it is a challenging task to obtain optimal performance for TPC-C evaluation on a large-scale high-end computer. In this paper, we designed and implemented a large-scale TPC-C evaluation system based on the latest TPC-C specification using solid-state drive (SSD) storage devices. By analyzing the characteristics of the TPC-C workload, we propose a series of system-level optimization methods to improve the TPC-C performance. First, we propose an approach based on SmallFile table space to organize the test data in a round-robin method on all of the disk array partitions; this can make full use of the underlying disk arrays. Second, we propose using a NOOP-based disk scheduling algorithm to reduce the utilization rate of processors and improve the average input/output service time. Third, to improve the system translation lookaside buffer hit rate and reduce the processor overhead, we take advantage of the huge page technique to manage a large amount of memory resources. Lastly, we propose a locality-aware interrupt mapping strategy based on the asymmetry characteristic of non-uniform memory access systems to improve the system performance. Using these optimization methods, we performed the TPC-C test on two large-scale high-end computers using SSD arrays. The experimental results show that our methods can effectively improve the TPC-C performance. For example, the performance of the TPC-C test on an Intel Westmere server reached 1.018 million transactions per minute.     

最小通路法在通信保密装备可靠性建模中的应用

针对通信保密装备可靠性建模难度大的问题,提出了一种新的适用于复杂系统的可靠性建模方法一最小通路法。通过在系统拓扑结构图上搜索出所有能够使系统正常工作的最小通路,建立系统的可靠性模型。该方法基于广义的网络拓扑结构,因此网络的源节点和目标节点不必局限于严格的定义,可以随意指定,具有很大的灵活性。实例证明,该方法可行有效。     

Effect of Sintering Temperature on Magnetic and Electrical Properties of GdBaCo<Subscript>2</Subscript><Emphasis Type="Italic">O</Emphasis><Subscript>5 + <Emphasis Type="Italic">δ</Emphasis></Subscript>

In this study, we report the results of an investigation into the sintering temperature dependence of magnetic and transport properties for GdBaCo₂ O _{5 + δ} synthesized through a sol-gel method. The lowering of sintering temperature leads to the increase of oxygen content and the reduction of grain size. The increase of oxygen content results in the enhancement of magnetic interactions and the weakening of Coulomb repulsion effect, while the reduction of grain size improves the magnetoresistance effect. Metal-insulator transition accompanied with spin-state transition is observed in all samples.     

基于Opencv的絮体颗粒跟踪与沉速测量系统研究

针对饮用水处理过程混凝剂投加量对处理结果的直接影响,提出了一个以絮体的沉降速度(作为主控,等效粒径、数量等参数作为辅控的多源数据融合的混凝剂投药模型。本文基于Open CV机器视觉库,以VS2010为平台,采用C++语言,编写絮体检测和沉降速度测量在线系统的软件,实现了絮体各个参数和沉降速度的实时监测。     

基于抗恶劣环境计算机的电磁兼容与热设计

为了解决抗恶劣环境计算机的电磁兼容与散热问题,通过对基于抗恶劣环境计算机电磁兼容与热设计的研究,提出了基于抗恶劣环境计算机电磁兼容与热设计方法。该方法中包括基于抗恶劣环境计算机电磁兼容与热设计的思路和实现过程。在该方法采用了仿真与测试的手段保证了设计的正确性。该方法已经投入应用,在应用过程中取得了良好的效果。     

塑料瓶贴标用乳液胶的研究

本文分析了塑料瓶的表面结构特性及其对贴标胶的要求，简介乳液胶的合成过程，讨论了聚会温度、搅拌速度、增粘剂和改性剂对贴标胶的影响。     

三相异步电动机起动方式的分析与选择

通过分析三相异步电动机各种起动方式的电压、电流、转矩的波形和特性,合理选择合适的起动方式。     

Investigation and minimization of underfill delamination in flip chip packages

A generalized plane strain condition is assumed for an edge interfacial crack between die passivation and underfill on an organic substrate flip chip package. C4 solder bumps are explicitly modeled. Temperature excursions are treated as loading conditions. The design factors studied include underfill elastic modulus, underfill coefficient of thermal expansion (CTE), fillet height, and die overhang. Varying underfill modulus and CTE produces a different stress field at underfill/die passivation interface, different stress intensity factor (SIF), and phase angle (/spl psi/) even under the same loading condition. The baseline case uses underfill with elastic modulus of 6 GPa, CTE of 36 ppm//spl deg/C and fillet height equal to half die thickness. Four more cases involving underfill material properties are investigated by varying elastic modulus between 3 and 9 GPa, and by varying CTE between 26 and 46 ppm//spl deg/C. The effect of fillet height is also studied by assuming no fillet and full fillet, i.e., fillet height equal to die thickness. Finally, two cases concerning the influence of die overhang, defined as the nominal distance between outermost solder joint and die edge, are investigated. Fracture parameters, including energy release rate (G) and phase angle (/spl psi/), are evaluated as a function of dimensions. Underfill material properties (elastic modulus and CTE), fillet configuration, and die overhang can be optimized to reduce the risk of underfill delamination in flip chip or direct chip attach (DCA) applications.