The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform

Reconfigurable computing offers a wide range of low cost and efficient solutions for embedded systems. The proper choice of the reconfigurable device, the granularity of its processing elements and its memory architecture highly depend on the type of application and their data flow. Existing solutions either offer fine grain FPGAs, which rely on a hardware synthesis flow and offer the maximum degree of flexibility, or coarser grain solutions, which are usually more suitable for a particular type of data flow and applications. In this paper, we present the MORPHEUS architecture, a versatile reconfigurable heterogeneous System-on-Chip targeting streaming applications. The presented architecture exploits different reconfigurable technologies at several computation granularities that efficiently address the different applications needs. In order to efficiently exploit the presented architecture, we implemented a complete software solution to map C applications to the reconfigurable architecture. In this paper, we describe the complete toolset and provide concrete use cases of the architecture.     

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization

Advanced nanometer technologies have led to a drastic increase in operational frequencies resulting in the performance of circuits becoming increasingly vulnerable to timing variations. The increasing process spread in advanced nanometer nodes poses considerable challenges in predicting post-fabrication silicon performance from timing models. Thus, there is a great need to qualify basic building structures on silicon in terms of critical parameters before they could be integrated within a complex System-on-Chip (SoC). The work of this paper presents a configurable circuit and an associated power-aware at-speed test methodology for the purpose of qualifying basic standard cells and complex IP structures to detect the presence of timing faults. Our design has been embedded within test-chips used for the development of the 28 nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The relevant silicon results and analysis validate the proposed power-aware test methodology for qualification and characterization of IPs and provide deeper insights for process improvements.     

Microstructure and texture analysis of narrow copper line versus widths and annealing for reliability improvement

In this article, we focus on the possible influence of interconnect Cu microstructure on electromigration phenomenon. First three annealing conditions were applied on interconnects. Microstructure and texture of copper were characterized by Electron BackScattered Diffraction (EBSD). Then electromigration tests have been carried out on 70 and 150 nm line widths of 45 nm node technology. In both cases no significant difference was observed in term of reliability performance versus annealing conditions. On the contrary large difference is observed on Electron BackScattered Diffraction results. Then, a statistical approach was used to investigate local microstructure and texture of copper for 150 nm line width. The results underline that morphological parameters of copper can vary versus annealing conditions but lead to similar reliability performances. We can thus conclude that these parameters are not in relationship with electromigration phenomena in these interconnects. On the other hand, high amount of misorientation has been highlighted as responsible of early failures.     

DUV-induced micro and nanopatterning of polymer plasma deposited films

A simple method is described for patterning polymer surfaces with reactive groups. This entails pulsed plasma deposition of anhydride functionalized films, followed by DUV irradiation using a ArF excimer laser. Micro and nano-scale patterning was demonstrated, leading to well defined structures with controlled chemistry and/or geometries. We investigated the chemical changes induced by DUV irradiation. Among other parameters, we demonstrated that the covalent attachment of an amine terminated nucleophile via the aminolysis improved significantly the DUV photosensitivity. Using this approach it was possible to create combinatorial patterned surfaces. In particular such patterned polymer films appear as excellent candidate to study the effect of nanostructuration on the development of biofilms.     

Behaviour of CPW and TFMS lines at high temperature for RF applications in sub-45 nm nodes

Coplanar waveguide (CPW) and thin film microstrip (TFMS) lines integrating porous ultra low-k as inter-metal dielectric layers (k = 2.5) and copper as metal, are for the first time experimentally measured up to 110 GHz and under different temperature conditions, up to 200 °C. The extracted attenuation and propagation coefficients of those transmission lines are compared to simulations performed with MAGWEL software, a frequency domain 3-D Maxwell solver. Based on the characterization results some guidelines related to interconnect design are presented for future applications.     

On the reduction of thermal and flicker noise in ENG signal recording amplifiers

Because of the extremely low amplitude of the input signal, the design of electro-neuro-graph (ENG) amplifiers involves a special care for flicker and thermal noise reduction. The task becomes really challenging in the case of implantable electronics, because power consumption is restricted to few hundreds μW. In this work, two different circuit techniques aimed to reduce flicker and thermal noise, in ultra-low noise amplifiers for implantable medical devices, are demonstrated. The circuit design, and measurement results are presented, in both cases showing an excellent performance, and noise to power consumption trade-off. In the first circuit, a very simple low-pass G_m–C chopper amplifier is used for flicker noise cancellation. It consumes only 28 mW, with a measured input referred noise and offset of 2  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ , and 2.5 μV, respectively. In the second circuit, a ultra-low noise amplifier, a energy-efficient DC–DC down-converter, and low voltage design techniques are combined, for the reduction of thermal noise with a minimum power consumption. Measured input referred noise in this case was 5.5  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ at only 380 μW power consumption. Both circuits were fabricated in a 1.5 μm technology.     

Hidden Markov Modeling of Error Patterns and Soft Outputs for Simulation of Wideband CDMA Transmission Systems

In this paper, a Hidden Markov Modeling (HMM) technique for a fast and accurate simulation of bit errors and soft outputs in wireless communication systems is presented. HMMs with continuous probability distributions are considered. Soft outputs and bit errors are combined to error patterns. We focus on binary phase–shift keying (BPSK) modulation for direct–sequence spread spectrum (code–division multiple access, CDMA) transmission as proposed e.g. for the third generation wireless communication system UMTS (uplink for the frequency division duplex mode (FDD)). Comparisons of simulated bit error rates for HMM models and Rake receivers are shown for AWGN, flat fading, and vehicular channel conditions. In order to assess the ability of the HMM to describe the dynamical behaviour of the channel a comparison for transmission with interleaving and convolutional coding is presented. Furthermore calculated autocorrelation functions of the error patterns and error gap distributions corresponding to the Rake receiver and to the HMM, respectively, are presented. Our investigations show a strong dependence of the required HMM order on E_b/N₀ and the channel conditions. The degree of accordance of the HMM outputs and the training data is examined based on calculated statistical scoring indicators.