Kinetic Monte Carlo simulations of radiation induced segregation and precipitation

Kinetics of radiation induced segregation and precipitation in binary alloys are studied by Monte Carlo simulations. The simulations are based on a simple atomic model of diffusion under electron irradiation, which takes into account the creation of point defects, the recombination of close vacancy-interstitial pairs and the point defect annihilation at sinks. They can reproduce the coupling between point defect fluxes towards sinks and atomic fluxes, which controls the segregation tendency. In pure metals and ideal solid solutions, the Monte Carlo results are found to be in very good agreement with classical models based on rate equations. In alloys with an unmixing tendency, we show how the interaction between the point defect distribution, the solute segregation and the precipitation driving force can generate complex microstructural evolutions, which depend on the very details of atomic-scale diffusion properties.     

Modelling diffusion-controlled kinetics in equilibrium and driven alloys

Summary We introduce a very simple model for thermally activated atomic migration on a lattice, and several techniques to handle it. For thermodynamical systems, the model can be used for simulating decomposition paths taking into account relevant metallurgical features. Close to equilibrium, the simplest mean-field approximation of the model can be linearized with respect to the departure from equilibrium; one then gets a microscopic interpretation of classical phenomenological coefficients, such as mobility, interfacial transfer coefficient, rate constants for the coupled relaxation of concentration and order fields. Further away from the equilibrium, the nonlinearities can be taken into account in a consistent way. For driven alloys, i.e. alloys submitted to external forcing, forced atomic migration is added to the model and new features emerge: the model is supported by several experimental results some of which confirmed its predictions a posteriori.     

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform

Reconfigurable computing offers a wide range of low cost and efficient solutions for embedded systems. The proper choice of the reconfigurable device, the granularity of its processing elements and its memory architecture highly depend on the type of application and their data flow. Existing solutions either offer fine grain FPGAs, which rely on a hardware synthesis flow and offer the maximum degree of flexibility, or coarser grain solutions, which are usually more suitable for a particular type of data flow and applications. In this paper, we present the MORPHEUS architecture, a versatile reconfigurable heterogeneous System-on-Chip targeting streaming applications. The presented architecture exploits different reconfigurable technologies at several computation granularities that efficiently address the different applications needs. In order to efficiently exploit the presented architecture, we implemented a complete software solution to map C applications to the reconfigurable architecture. In this paper, we describe the complete toolset and provide concrete use cases of the architecture.     

Variational implicit surface meshing

In this paper, we propose a new algorithm to mesh implicit surfaces which produces meshes both with a good triangle aspect ratio as well as a good approximation quality. The number of vertices of the output mesh is defined by the end-user. For this goal, we perform a two-stage processing: an initialization step followed by an iterative optimization step. The initialization step consists in capturing the surface topology and allocating the vertex budget. The optimization algorithm is based on a variational vertices relaxation and triangulation update. In addition a gradation parameter can be defined to adapt the mesh sampling to the curvature of the implicit surface. We demonstrate the efficiency of the approach on synthetic models as well as real-world acquired data, and provide comparisons with previous approaches.     

Multi-heuristic scheduling: three approaches to tune compromises

Most of the available industrial schedulers are based on a simulation approach using dispatching rules. These rules are often dedicated to the satisfaction of a single performance criterion, and are used whatever the characteristics of the workshop or of the set of jobs. An approach which allows one to bring in compromises between rules is set out in this paper. These compromises can be parametered in accordance with the objectives of the workshop and the characteristics of the jobs in order to introduce some reactivity in the decision system. Three ways to set up the parameters are compared: experimental design, fuzzy expert system and neural network. The method allowing one to define compromises can be implemented on each scheduler that uses a simulation approach. Tests have been made with an industrial scheduler called SIPAPLUS, the results of which are developed in this paper.     

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization

Advanced nanometer technologies have led to a drastic increase in operational frequencies resulting in the performance of circuits becoming increasingly vulnerable to timing variations. The increasing process spread in advanced nanometer nodes poses considerable challenges in predicting post-fabrication silicon performance from timing models. Thus, there is a great need to qualify basic building structures on silicon in terms of critical parameters before they could be integrated within a complex System-on-Chip (SoC). The work of this paper presents a configurable circuit and an associated power-aware at-speed test methodology for the purpose of qualifying basic standard cells and complex IP structures to detect the presence of timing faults. Our design has been embedded within test-chips used for the development of the 28 nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The relevant silicon results and analysis validate the proposed power-aware test methodology for qualification and characterization of IPs and provide deeper insights for process improvements.     

Microstructure and texture analysis of narrow copper line versus widths and annealing for reliability improvement

In this article, we focus on the possible influence of interconnect Cu microstructure on electromigration phenomenon. First three annealing conditions were applied on interconnects. Microstructure and texture of copper were characterized by Electron BackScattered Diffraction (EBSD). Then electromigration tests have been carried out on 70 and 150 nm line widths of 45 nm node technology. In both cases no significant difference was observed in term of reliability performance versus annealing conditions. On the contrary large difference is observed on Electron BackScattered Diffraction results. Then, a statistical approach was used to investigate local microstructure and texture of copper for 150 nm line width. The results underline that morphological parameters of copper can vary versus annealing conditions but lead to similar reliability performances. We can thus conclude that these parameters are not in relationship with electromigration phenomena in these interconnects. On the other hand, high amount of misorientation has been highlighted as responsible of early failures.