PIXHAWK: A micro aerial vehicle design for autonomous flight using onboard computer vision

We describe a novel quadrotor Micro Air Vehicle (MAV) system that is designed to use computer vision algorithms within the flight control loop. The main contribution is a MAV system that is able to run both the vision-based flight control and stereo-vision-based obstacle detection parallelly on an embedded computer onboard the MAV. The system design features the integration of a powerful onboard computer and the synchronization of IMU-Vision measurements by hardware timestamping which allows tight integration of IMU measurements into the computer vision pipeline. We evaluate the accuracy of marker-based visual pose estimation for flight control and demonstrate marker-based autonomous flight including obstacle detection using stereo vision. We also show the benefits of our IMU-Vision synchronization for egomotion estimation in additional experiments where we use the synchronized measurements for pose estimation using the 2pt+gravity formulation of the PnP problem.     

Studies on Helium Liquids by Vibrating Wires and Quartz Tuning Forks

We present results of low-temperature experiments on dilute mixtures of ³He in ⁴He and on pure ³He, obtained by means of two kinds of mechanical oscillators immersed in the liquid sample: vibrating wires and quartz tuning forks. The helium sample was cooled either by adiabatic demagnetization of an immersed copper nuclear stage or by adiabatic melting of ⁴He in superfluid ³He. The measured effect of the surrounding fluid on the mechanical resonance of the oscillators is compared with existing theories. We also discuss resonances of second sound and the state of supersaturation, both observed by a tuning fork in helium mixtures.     

Fabrication of Ni-shims using UV-moulding as an intermediate step

We fabricated nickel-shims including various types of structures with dimensions from hundreds of nanometers to several microns. The mastering process was made by electron-beam lithography, lift-off and reactive ion etching techniques. Then the structures were copied into a UV-curable ORMOCER-material and the Ni-shims were fabricated by electroforming using UV-copies as masters. The experiments showed that the use of UV-copying evades typical quartz master sticking and cracking problems. Furthermore, all features were replicated in the final Ni-shim as they existed in the quartz master proving the method suitable for the fabrication of the Ni-shims from the quartz masters with high precision.     

On Design of Parallel Memory Access Schemes for Video Coding

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.Jarno K. Tanskanen was born in Joensuu, Finland in 1975. He studied analog and digital electronics in the Department of Electrical Engineering, and computer architecture in the Department of Information Technology at Tampere University of Technology, where he received his M.Sc. degree in 1999. He is currently working as a research scientist in the Institute of Digital and Computer Systems at TUT. His Dr.Tech. research concerns parallel processing of video compression. jarno.tanskanen@tut.fiReiner Creutzburg received his Diploma in Mathematics in 1976 and attained his Ph.D. in Mathematics in 1984 from the Rostock University, Germany. Prof. Creutzburg has published 3 books, filed 2 patents, and produced approximately 100 articles, preprint, and conference papers. Professional Experience: Since 2000—Part-time Professor for Multimedia technology, Tampere University of Technology, Finland. Since 1992—Full-time Professor of Computer Science, Fachhochschule Brandenburg-University of Applied Sciences, Brandenburg, Germany. 1990 to 1992—Assistant Professor, University of Karlsruhe, Institute of Algorithms and Cognitive Systems, Germany. 1987 to 1989—Head of the Research Section Image Processing. 1986 to 1989—Founder and Head of the International Base Laboratory of Image Processing and Computer Graphics for East European countries at the Central Institute of Cybernetics and Information Processes of the Academy of Sciences (Berlin), Germany. 1976 to 1989—Researcher and Assistant Professor in various Universities and the Academy of Sciences, Central Institute of Cybernetics and Information, Berlin. creutzburg@fh-brandenburg.deJarkko T. Niittylahti was born in Orivesi, Finland, in 1962. He received the M.Sc, Lic.Tech, and Dr.Tech degrees at Tampere University of Technology (TUT) in 1988, 1992, and 1995, respectively. From 1987 to 1992, he was a researcher at TUT. In 1992–93, he was a researcher at CERN in Geneva, Switzerland. In 1993–95, he was with Nokia Consumer Electronics, Bochum, Germany, and in 1995–97 with Nokia Research Center, Tampere, Finland. In 1997–2000, he was a Professor at Signal Processing Laboratory, TUT, and in 2000–2002 at Institute of Digital and Computer Systems, TUT. Currently, he is a Docent of Digital Techniques at TUT and the managing director of Staselog Ltd. He is also a co-founder and President of Atostek Ltd. He is interested in designing digital systems and architectures. jarkko.niittylahti@tut.fi     

A 700 MHz laser radar receiver realized in 0.18 μm HV-CMOS

This study presents a CMOS receiver chip realized in 0.18 µm High-Voltage CMOS (HV-CMOS) technology and intended for high precision pulsed time-of-flight laser range finding utilizing high-energy sub-ns laser pulses. The IC chip includes a trans-impedance preamplifier, a post-amplifier and a timing comparator. Timing discrimination is based on leading edge detection and the trailing edge is also discriminated for measuring the width of the pulse. The transimpedance of the channel is 25 kΩ, the uncompensated walk error is 470 ps in the dynamic range of 1:21,000 and the input referred equivalent noise current 450 nA (rms).     

On-chip offset generator for accurate integral non-linearity testing of A/D converters and D/A-A/D converter pairs

It has recently shown how a constant dc offset between two low-quality test signals can be used to test the integral nonlinearity (INL) of A/D converters (ADCs) without an accurate test stimulus, and how the same method can be used to test the INL of D/A converters (DACs) as well. We propose here an on-chip offset generator for producing the constant offset and analyse its limitations. Experimental tests on the 122 × 22 μm² offset generator fabricated in 130 nm CMOS process show that it can be used to test the INL of 12-b DACs and ADCs. The generator is rail-to-rail capable so that almost the whole input/output range of converters can be tested. Moreover, if the proposed offset generator is used in a ratiometric test setup as proposed here as well, the influence of a reference voltage drift on measurement accuracy is cancelled out. Because of its small size, simple design, rail-to-rail capability and immunity to reference voltage changes, the proposed offset generator is well suited for built-in self-test usage.     

Comparison of Two Integrated BiCMOS 950 MHz Direct I/Q Modulators

Two integrated direct I/Q modulators suitable for directupconversion with an output frequency of 950 MHz and baseband frequencies of60 to 500 kHz are fabricated in a 1.2 µm and 0.8 µm BiCMOSprocess, respectively, and their performance under various operatingconditions is discussed. The modulators use different phase shiftertopologies, one of which is based on digital CML latches and the other ondifferential pairs with resistive and capacitive emitter degeneration. Bothcircuits are operated using a single 5 V supply and they consume 50 mA or115 mA depending on the topology. The main properties of the CML modulatorare, for example, an output power of –11 ± 0.5 dBm at 100 MHzand –15 ± 2.25 dBm at 950 MHz over the temperature range of–10 to +85°C, LO suppression of 38 dBc and image rejection of41 dBc.     

Integrated Time-to-Digital Converters Based on Interpolation

The main features of two time-to-digital convertersbased on interpolation are presented, together with some measurementresults. The first converter is based on digital delay line interpolatorsand has been implemented in a 1.2 µm CMOS process.It has a single-shot resolution of 1 ns (-value)and a nonlinearity less than ±50 ps in the measurementrange 5 to 500 ns. The power consumption of the circuit is 15mW. The second time digitizer has analog interpolators basedon time-to-voltage conversion and has been implemented in a 1.2 µm BiCMOS process. It has a single-shot resolutionof 50 ps and a nonlinearity less than 150 ps in the measurementrange 1 to 300 ns. The power consumption of this circuit is 200mW.     

Considerations for Synchronization in Body Area Networks for Human Activity Monitoring

In this paper, we highlight considerations for synchronization issues in body area networks. Requirements for the synchronization accuracy in body area networks depend on the application at hand. Synchronization may be needed for power management, sample ordering, calculation of stimulus responses and for sensor fusion. This paper provides a theoretical exercise to help understand the accuracy required for typical human motion sensing. It gives an overview of various synchronisation strategies used and implemented in prototype systems. Lessons learnt from practical implementations using Bluetooth, an IEEE 802.15.4 proprietary network and Nanonet are presented to illustrate the principles involved. The discussion provides some considerations and the requirements for typical WBAN applications.