Parasitic-aware analytical modeling of integrated CMOS inductively degenerated narrow-band low noise amplifiers

In this paper, we present an analytical modeling methodology for fully integrated inductively-degenerated CMOS narrow-band cascode Low Noise Amplifiers (LNA) that captures short channel transistor effects to enable rapid design space exploration in current and future process technologies. The modeling methodology captures the impact of parasitics on passive components, ESD-protection structures, and devices to accurately predict both impedance matching and noise figure. Our modeling is suitable for numerical optimization and fully automated synthesis for LNAs. The results indicate that the methodology models ESD-protected LNA circuits with 47.9% better accuracy in noise figure when compared with several current analytical modeling techniques with four orders of magnitude improvement in simulation time over circuit-level simulation. Given its speed and accuracy, the analytical modeling methodology is well-suited for design space exploration.     

Analytical wide-band modeling of high frequency resistance in integrated spiral inductors

For integrated spiral inductor synthesis, designers and design automation tools require efficient modeling techniques during the initial design space exploration process. In this paper, we introduce an analytical frequency-dependent resistance model for integrated spiral inductors. Based on our resistance formulation, we have developed a systematic technique for creating wide-band circuit models for accurate time domain simulation. The analytical resistance model provides a fast alternative to field solver-based approaches with typical errors of less than 2.6 percent while surpassing the accuracy of several other analytical modeling techniques by an order of magnitude. Furthermore, the wide-band circuit generation technique captures the frequency-dependent resistance of the inductor with typical errors of less than 3.2 percent.     

Flexible Prime‐Field Genus 2 Hyperelliptic Curve Cryptography Processor with Low Power Consumption and Uniform Power Draw

This paper presents an energy‐efficient (low power) prime‐field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a 0.13 μm standard CMOS technology, performs an 81‐bit divisor multiplication in 503 ms consuming only 6.55 μJ of energy (average power consumption is 12.76 μW). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.     

Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes

Soft-edge flip-flop (SEFF) based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by enabling the opportunistic time borrowing. The application of this technique to the near-threshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections. In particular, delay lines in SEFFs have to be over-designed to provide larger transparency windows to overcome the variation in path delays, which causes them to consume more power. To address this issue, this paper presents a novel way of designing delay lines in SEFFs to have a large enough transparency window size and low power consumption. Two types of linear pipeline design problems using the SEFFs are formulated and solved: (1) designing energy-delay optimal pipelines for the general usage that requires SEFFs to operate in both the near-threshold and super-threshold regimes, and (2) designing minimum energy consumed pipelines for particular use case with a minimum operating frequency constraint. Design methods are presented to derive requisite pipeline design parameters (i.e., depth and sizing of delay lines in SEFFs) and operating conditions (i.e., supply voltage and operating frequency of the design) in presence of process-induced variations. HSPICE simulation results using ISCAS benchmarks demonstrate the efficacy of the presented design methods.     

Design techniques for reducing the impact of component variations on narrow-band low noise amplifiers

Given the increasing demand for integrated wireless systems in system-on-chip technology, narrow-band low noise amplifier (LNA) designs must be robust against variations in device parameters and passive component values to improve manufacturing yield for high volume applications. In this paper, we develop two design techniques for reducing the impact of component variations on narrow-band LNA performance. The results demonstrate that by increasing the bandwidth of the narrow-band LNA and applying more conservative design constraints, we can mitigate the reliability implications of process variations on impedance matching, gain, and power consumption.     

Multi-Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 μm. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 μW.     

Efficient multisecret sharing scheme using new proposed computational security model

A multisecret sharing (MSS) is a method for sharing a set of secrets among some participants. They can recover each of these secrets without endangering the other secrets. Two kinds of security models have been proposed for MSS schemes. These models are categorized into 2 types. The first security model is unconditional security. This approach decreases the efficiency of MSS schemes. Therefore, the second type of security, which is more relaxed, appeared. This approach is called computational security. In this paper, with 2 examples, we will show that the current definition of computational security does not satisfy all of our expectations from a secure MSS scheme. In fact, in these examples, recovering a secret leaks information to the other secrets while these schemes are considered secure in view of the computational security. After determining the shortcomings of the current security definition, we propose a new definition for computational security and present an MSS scheme that enjoys rigorous proof of security in terms of the new definition. In addition, a complete comparison in terms of share size, number of public values, and required operations for recovering a secret between our scheme and previous schemes indicates that the presented scheme is efficient.     

Two-dimensional random projection

As an alternative to adaptive nonlinear schemes for dimensionality reduction, linear random projection has recently proved to be a reliable means for high-dimensional data processing. Widespread application of conventional random projection in the context of image analysis is, however, mainly impeded by excessive computational and memory requirements. In this paper, a two-dimensional random projection scheme is considered as a remedy to this problem, and the associated key notion of concentration of measure is closely studied. It is then applied in the contexts of image classification and sparse image reconstruction. Finally, theoretical results are validated within a comprehensive set of experiments with synthetic and real images.     

On the necessary and sufficient requirement of a CIOQ switch to emulate an Output Queued switch

There has been much interest to emulate the behavior of Output Queued switches. The early result of such attempts was reported by Prabhakar and McKeown using the CIOQ switches with speedup factor of 4. Subsequently, Stoica and Zhang and independently Chuang et al. showed that a speedup of 2 in conjunction with their scheduling schemes would be sufficient for CIOQ switches to emulate Output Queued switches.Additionally, Chuang et al. showed that in “Average Sense” a speedup of 2?1/N is necessary and sufficient for CIOQ to emulate Output Queued switch behavior.Our paper reports that in the “Strict Sense” a speedup of 2 is both necessary and sufficient. We show this requirement using examples for 2x2 and 3x3 switches. Then, with a constructed traffic pattern, it is proved that in the “Strict Sense” a speedup of 2 is necessary to emulate the behavior of an Output Queued switch for any switch size N.Combining this result with the previous scheduling schemes, we conclude that in the “Strict Sense”, a speedup of 2 is the necessary and sufficient condition to emulate the behavior of an Output Queued switch, using a CIOQ switch.Additionally, easing the assumptions and allowing the packet segmentation, it is shown that the speedup requirement to emulate the behavior of an Output Queued switch can be reduced to values even smaller than 2?1/N. For this case a lower bound of 3/2 and an upper bound of 2 is proved.     

Antimicrobial Property,Antioxidant Capacity,and Cytotoxicity of Essential Oil from Cumin Produced in Iran

ABSTRACT: Cumin (Cuminum cyminum) is one of the commonly used spices in food preparations. It is also used in traditional medicine as a stimulant, a carminative, and an astringent. In this study, we characterized the antimicrobial, antioxidant, and cytotoxic activities of cumin. E. coli, S. aureus, and S. faecalis were sensitive to various oil dilutions. The total phenol content of the essential oil was estimated to be 33.43 μg GAE/mg of the oil. The oil showed higher antioxidant activity compared with that of BHT and BHA. The cumin essential oil exhibited a dose-dependent scavenging of DPPH radicals and 5.4 μg of the oil was sufficient to scavenge 50% of DPPH radicals/mL. At a concentration of 0.1 μL/mL, oil destructed Hela cells by 79%. The antioxidant activity of cumin essential oil might contribute to its cytotoxic activity. Acute and subchronic toxicity was studied in a 30-d oral toxicity study by administration to Wistar rats of the essential oil. A 17.38% decrease in WBCs count, and 25.77%, 14.24%, and 108.81% increase in hemoglobin concentration, hematocrit, and platelet count, respectively, were noted. LDL/HDL ratio was reduced to half, which adds to the nutritional effects of cumin. Thus, cumin with a high phenolic content and good antioxidant activity can be supplemented for both nutritional purposes and preservation of foods.