Fault-aware Communication Mapping for NoCs with Guaranteed Latency

As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmission of messages, such that designer-imposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statically assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. First, we reduce the total amount of transmitted messages, and, second, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arrival probability and guaranteed worst case application response time.     

Polarization independent isolator using spatial walkoff polarizers

A novel type of polarization-independent optical isolator is described which utilizes the polarization walkoff provided by birefringent crystals. Isolation of 44 dB is measured at a wavelength of 1.3 mu m with single-mode fiber insertion loss of 1.5 dB. A temperature-independent scheme is also described that provides at least 39 dB of isolation over the temperature range of 25-75 degrees C.<>     

Obtaining high-alumina cement at the semiluksk refractories factory

Conclusions We demonstrate that it is, in principle, possible to obtain refractory high-alumina cement on industrial equipment at the Semiluksk refractories factory. Technological parameters were developed for preparing raw mixtures, pressing the green articles and firing in a tunnel kiln. It was established that the mass percentage of SiO₂ in the raw mixture should not exceed 1.5%. For industrial production of high-alumina cement in department No. 1 it is necessary to implement measures on the mechanization of the production process.Translated from Ogneupory, No. 5, pp. 26–28, May, 1986.     

Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures

Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the high availability required for these tasks, it is necessary to incorporate mechanisms for error detection and recovery. Correct operation of the memory system is defined by the memory consistency model. Errors can therefore be detected by checking if the observed memory system behavior deviates from the specified consistency model. Based on recent work, we design a framework for dynamic verification of memory consistency (DVMC). The framework consists of mechanisms to verify three invariants that are proven to guarantee that a specified memory consistency model is obeyed. We describe an implementation of the framework for the SPARCv9 architecture, and we experimentally evaluate its performance using full-system simulation of commercial workloads.     

Slip in Vibrating Wire Experiments on 3He-4He Mixtures

No Heading We present vibrating wire viscometer experiments in concentrated and dilute ³He-⁴He mixtures showing that the slip length may become orders of magnitude larger than the mean free path due to increased specular scattering of the ³He quasiparticles with the superfluid ⁴He film on the wire. The experimental results are in good agreement with a recent theory for slip which accounts for the cylindrical geometry of the wire and for velocity slip in directions normal as well as tangential to the surface of the wire.PACS numbers: 67.60.Fp, 51.20.+d     

Skin Inflammation Modulation via TNF-α, IL-17, and IL-12 Family Inhibitors Therapy and Cancer Control in Patients with Psoriasis

The systemic inflammatory syndrome concept is one of the foundations that stand at the basis of revolutionary modern and future therapies, based on the in-depth understanding of the delicate mechanisms that govern the collaboration between the systems and organs of the human body and, at the same time, the fine balance that ensures a reproach-free operation. An interesting concept that we propose is that of the environment-inadequacy status, a concept that non-specifically incorporates all the situations of the organism’s response disorders in the face of imprecisely defined situations of the environment. The correlation between these two concepts will define the future of modern medicine, along with the gene-adjustment mechanisms. Psoriasis is a clear example of an inadequate body response as a result of exposure to as of yet undefined triggers with an excessive systemic inflammatory reaction and hitherto insufficiently controllable. Modern biological therapies, such as TNF-α, IL-12 family, and IL-17 inhibitors, are intended to profoundly reshape the cytokine configuration of patients with inflammatory diseases such as psoriasis, with tremendous success in disease control. Yet, because of the important roles of cytokines in cancer promotion and control, concern was raised about the fact that the use of biologicals may alter immune surveillance and promote cancer progression. Both theoretical and practical data nevertheless showed that the treatment-induced control of cytokines may be beneficial for reducing the inflammatory milieu that promotes cancer and such have a beneficial role in maintaining health. We briefly present the intricate roles of those cytokine families on cancer control, with some debates on if their inhibition might or might not promote additional tumoral development.     

Cyclic invariance for discrete time-delay systems

This technical communique introduces a new concept of set invariance with respect to linear discrete time dynamics affected by delay. We are interested in the definition and characterization of sequences of cyclically invariant subsets in the state space. The algebraic conditions established in the late ’80s for linear dynamics are generalized to invariance analysis in the presence of delays for given sequences of polyhedral sets.     

The meta-stable dip (MSD) effect in SOI FinFETs

The meta-stable dip (MSD) effect is demonstrated and characterized in SOI FinFETs. With ascending scan of front-gate voltage (V_G1), the magnitude of drain current (I_D) tends to be fixed within a specific region of the front-gate voltage and this leads to a dip of transconductance (g_m). The dip width can be modulated through a control of bias condition or measurement speed such as back-gate voltage (V_G2), drain voltage (V_D) and step size of the front-gate voltage. From the dual-gate transient measurement, it is found that the MSD effect is highly dependent on the floating-body effect. In SOI FinFETs, the MSD effect is significantly affected by the fin width due to the fringing electric field of the lateral gates.     

A comparison of MOSFETs aging under d.c., a.c. and alternating stress conditions

The effects of static, alternating and dynamic stress conditions on the degradation rate of 0.8μm n- and p-channel LDD MOS transistors have systematically been investigated and compared. The shifts of the threshold voltage, transconductance, linear drain current and charge pumping current were used to monitor the transistor degradation. The results suggest that the aging induced by a dynamic stress cannot be directly explained with static stress models, essentially because it is highly dependent on a larger number of parameters (biases and durations of the top and bottom levels of the pulses, transient times). The correlation of static and dynamic stresses also clarifies the degradation mechanisms, in particular the role of hot holes in the generation of interface states.     

IEEE-Compliant IDCT on FPGA-Augmented TriMedia

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.Mihai Sima was born in Bucharest, Romania. He received the MS degree in Electrical Engineering from Politehnica University of Bucharest, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had been with the Microelectronics Company in Bucharest for 3 years, where he was involved in instrumentation electronics for integrated circuit testing. Subsequently, he joined the Telecommunications Department of Politehnica University of Bucharest, where he had been involved in digital signal processing and speech recognition for 6 years. More recently, he had been with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, where he worked on reconfigurable architectures for mediaprocessing domain. He is currently an assistant professor with the Department of Electrical and Computer Engineering, University of Victoria, B.C., Canada. His research interests include computer architecture, reconfigurable computing, embedded systems, digital signal processing, and speech recognition.Sorin D. Coofan was born in Mizil, Romania. He received the MS degree in Computer Science from the Politehnica University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had worked with the Research & Development Institute for Electronic Components (ICCE) in Bucharest for a decade, being involved in structured design of digital systems, design rule checking of ICs layout, logic and mixed-mode simulation of electronic circuits, testability analysis, and image processing. He is currently an associate professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. His research interests include computer arithmetic, parallel architectures, embedded systems, reconfigurable computing, nano-electronics, neural networks, computational geometry, and computer aided design.Jos T.J. van Eijndhoven was born in Roosendaal, The Netherlands. He studied Electrical Engineering at the Eindhoven University of Technology, The Netherlands, obtaining the M.Sc. and Ph.D. degrees in 1981 and 1984, respectively, for a work on piecewise linear circuit simulation. Then, he became a senior research member in the design automation group of the Eindhoven University of Technology. In 1986 he spent a sabbatical period at the IBM Thomas J. Watson Research Laboratory, Yorktown Heights, New York, for research on high level synthesis. In 1998 he joined Philips Research Laboratories in Eindhoven, The Netherlands, to work on the architectural design of programmable multimedia hardware and the associated mapping of media processing applications.Stamatis Vassiliadis was born in Manolates, Samos, Greece. He is a professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. He has also served in the faculties of Cornell University, Ithaca, NY, and the State University of New York (S.U.N.Y.), Binghamton, NY.He hadworked for a decade with IBM in the AdvancedWorkstations and Systems laboratory in Austin TX, the Mid-Hudson Valley Laboratory in Poughkeepsie, NY, and the Glendale Laboratory in Endicott, NY. In IBM he was involved in a number of projects regarding computer design, organizations, and architectures and the leadership to advanced research projects. A number of his design and implementation proposals have been implemented in commerciallyavailable systems and processors including the IBM 9370 model 60 computer system, the IBM POWER II, the IBM AS/400 Models 400, 500, and 510, Server Models 40S and 50S, the IBM AS/400 Advanced 36, and the IBM S/390 G4 and G5 computer systems. For his work, he received numerous awards including 23 levels of Publication Achievement Awards, 15 levels of Invention Achievement Awards and an Outstanding Innovation Award for Engineering/Scientific Hardware Design in 1989. In 1990 he has been awarded the highest number of USA patents in IBM, six of his 70 USA patents being rated with the highest patent ranking in IBM.Kees A. Vissers graduated the Delft University of Technology, receiving his M.Sc. in 1980. He started directly with Philips Research Laboratories in Eindhoven where he was involved in highlevel simulation and high-level synthesis. He had been heading the research on hardware/software co-design and system level design for many years, and had a significant contribution to the TriMedia VLIW processor. From 1987 till 1988 he was a visiting researcher at Carnegie Mellon University, Pittsburgh, Pennsylvania, with the group of Don Thomas. He is currently a Research Fellow with University of California at Berkeley, Department of Electrical Engineering and Computer Sciences. His research interests include video processing, embedded media processing systems, and reconfigurable computing.