An investigation into physicochemical characteristics of ash produced from combustion of oil palm biomass wastein a boiler

Ash derived from combustion of Malaysian oil palm biomass (empty fruit bunches consisting of fibers) was physically and chemically characterized in order to provide a comprehensive understanding of its specific properties in terms of toxicity, compositions and reusability. Principal analyses conducted include particle size distribution, scanning electron microscopy, elemental dispersive X-ray, elemental analysis, toxicity characteristic leaching procedure (TCLP) as well as thermogravimetric, X-ray diffractometry and Fourier-transform infrared analyses. TCLP result indicated that the oil palm ash (OPA) should not be classified as toxic wastes in terms of heavy metal leachability since leachable copper, cadmium, lead and nickel concentrations were detected below the stipulated leachability limits. It was determined that the OPA contained high amount of potassium as well as presence of silica which implied its suitability to be reused as crude fertilizer or cement replacement material.     

Local calibration of rigid pavement performance models using resampling methods

The performance prediction models in the Pavement-ME design software are nationally calibrated using in-service pavement material properties, pavement structure, climate and truck loadings, and performance data obtained from the Long-Term Pavement Performance programme. The nationally calibrated models may not perform well if the inputs and performance data used to calibrate those do not represent the local design and construction practices. Therefore, before implementing the new M-E design procedure, each state highway agency (SHA) should evaluate how well the nationally calibrated performance models predict the measured field performance. The local calibrations of the Pavement-ME performance models are recommended to improve the performance prediction capabilities to reflect the unique conditions and design practices. During the local calibration process, the traditional calibration techniques (split sampling) may not necessarily provide adequate results when limited number of pavement sections are available. Consequently, there is a need to employ statistical and resampling methodologies that are more efficient and robust for model calibrations given the data related challenges encountered by SHAs. The main objectives of the paper are to demonstrate the local calibration of rigid pavement performance models and compare the calibration results based on different resampling techniques. The bootstrap is a non-parametric and robust resampling technique for estimating standard errors and confidence intervals of a statistic. The main advantage of bootstrapping is that model parameters estimation is possible without making distribution assumptions. This paper presents the use of bootstrapping and jackknifing to locally calibrate the transverse cracking and IRI performance models for newly constructed and rehabilitated rigid pavements. The results of the calibration show that the standard error of estimate and bias are lower compared to the traditional sampling methods. In addition, the validation statistics are similar to that of the locally calibrated model, especially for the IRI model, which indicates robustness of the local model coefficients.     

DVCC-Based Non-linear Feedback Neural Circuit for?Solving System of Linear Equations

A neural circuit to solve a system of simultaneous linear equations is presented. The circuit employs non-linear feedback to achieve a transcendental energy function that ensures fast convergence to the exact solution while enjoying reduction in hardware complexity over existing schemes. A new building block for analog signal processing, the digitally controlled differential voltage current conveyor (DC-DVCC) is introduced and is utilized for the non-linear synaptic interconnections between neurons. The proof of the energy function has been given and it is shown that the gradient network converges exactly to the solution of the system of equations. PSPICE simulation results are presented for linear systems of equations of various sizes and are found to be in close agreement with the algebraic solution. The use of CMOS DC-DVCCs and operational amplifiers facilitates monolithic integration.     

Scanning and Address Allocation Delays in Vehicular Communications

WLAN-based roadside-to-vehicle communications is an increasingly popular research trend. This paper examines the applicability of WLANs in the Intelligent Transportation Systems with focus on reducing the scanning phase delay and the address allocation delay. The handover delays become intolerable when the indoor WLAN Access Poins are accessed from by the outdoor mobile nodes at vehicular speeds. In this work, we propose a baseline scheme which calls for passively scanning only the orthogonal channels to reduce the scanning phase delay in the overall handover latency. We argue that the interference free orthogonal channels are ideal for conveying time critical information in vehicular environments. Secondly, this paper evaluates the delays incurred by the Dynamic Host Configuration Protocol (DHCP) in the handover process. The focus on establishing the amount of delay contributed by each DHCP phase and make some meaningful comments at the end. The conclusions made in this paper are based on real-world experiments and tests.     

Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis

The application of current generation computing machines in safety-centric applications like implantable biomedical chips and automobile safety has immensely increased the need for reviewing the worst-case error behavior of computing devices for fault-tolerant computation. In this work, we propose an exact probabilistic error model that can compute the maximum error over all possible input space in a circuit-specific manner and can handle various types of structural dependencies in the circuit. We also provide the worst-case input vector, which has the highest probability to generate an erroneous output, for any given logic circuit. We also present a study of circuit-specific error bounds for fault-tolerant computation in heterogeneous circuits using the maximum error computed for each circuit. We model the error estimation problem as a maximum a posteriori (MAP) estimate [28] and [29], over the joint error probability function of the entire circuit, calculated efficiently through an intelligent search of the entire input space using probabilistic traversal of a binary Join tree using Shenoy-Shafer algorithm [20] and [21]. We demonstrate this model using MCNC and ISCAS benchmark circuits and validate it using an equivalent HSpice model. Both results yield the same worst-case input vectors and the highest percentage difference of our error model over HSpice is just 1.23%. We observe that the maximum error probabilities are significantly larger than the average error probabilities, and provides a much tighter error bounds for fault-tolerant computation. We also find that the error estimates depend on the specific circuit structure and the maximum error probabilities are sensitive to the individual gate failure probabilities.     

Dose control circuit for digital electrostatic electron-beam array lithography

This paper demonstrates a technique for controlling the electron emission of an array of field emitting vertically aligned carbon nanofibers (VACNFs). An array of carbon nanofibers (CNF) is to be used as the source of electron beams for lithography purposes. This tool is intended to replace the mask in the conventional photolithography process by controlling their charge emission using the “Dose Control Circuitry” (DCC). The large variation in the charge emitted between CNFs grown in identical conditions forced the controller design to be based on fixed dose rather than on fixed time. Compact digital control logic has been designed for controlling the operation of DCC. This system has been implemented in a 0.5 μm CMOS process. Chandra Sekhar A. Durisety received his B.E. (Hons.) Instrumentation from Birla Institute of Technology and Sciences, Pilani, India in 1997 and his M.S in Electrical Engineering from University of Tennessee, Knoxville in 2002. Since 2003, he has been working towards his Ph.D degree also in Electrical Engineering at Integrated Circuits and Systems Lab (ICASL), University of Tennessee, Knoxville. He joined Wipro Infotech Ltd, Global R & D, Bangalore, India in 1997, where he designed FPGA based IPs for network routers. Since 1999, he was involved in the PCI bridge implementation at CMOS chips Inc, Santa Clara, CA, and the test bench development for Sony’s MP3 player, while at Toshiba America Electronic Components Inc., San Jose, CA. His research interests include multi-stage amplifiers, data converters, circuits in SOI and Floating Gate Devices. Rajagopal Vijayaraghavan received the B.E degree in electronics and communication engineering from Madras University in 1998 and the M.S degree in electrical engineering from the University of Texas, Dallas in 2001.He is currently working towards the Ph.D degree in electrical engineering at the University of Tennessee. His research interest is in the area of CMOS Analog and RF IC design. His current research focuses on LNAs and VCOs using SOI based MESFET devices. Lakshmipriya Seshan was born in Trivandrum, India on April 30, 1979. She received her B.tech in Electronincs & Communication Engg from Kerala University, India in June 2000 and M.S in Electrical Engg from University of Tennessee in 2004. In 2004, she joined Intel Corporation as an Analog Engineer, where she is engaged in the design of low power, high speed analog circuits for various I/O interface topologies. Syed K. Islam received his B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET) and M.S. and Ph.D. in Electrical and Systems Engineering from the University of Connecticut. He is presently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Tennessee, Knoxville. Dr. Islam is leading the research efforts of the Analog VLSI and Devices Laboratory at the University of Tennessee. His research interests are design, modeling and fabrication of microelectronic/optoelectronic devices, molecular scale electronics and nanotechnology, biomicroelectronics and monolithic sensors. Dr. Islam has numerous publications in technical journals and conference proceedings in the areas of semiconductors devices and circuits. Benjamin J. Blalock received his B.S. degree in electrical engineering from The University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at The University of Tennessee where he directs the Integrated Circuits and Systems Laboratory (ICASL). His research focus there includes analog IC design for extreme environments (both wide temperature and radiation immune), multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, mixed-signal/mixed-voltage circuit design for systems-on-a-chip, and bio-microelectronics. Dr. Blalock has co-authored over 60 published refereed papers. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems Inc.     

Multiattribute‐based routing for lifetime maximization in opportunistic mobile social networks

With the advancement in wireless technology and portable devices, smart phones have become one of the belongings of human being. People share their data online, but it has limitations due to transmission range and mobility. Yet opportunistic mobile social network enables users to share data online even if there is no connected path between source and destination. The widespread use of mobile phones equipped with WiFi, Bluetooth, and several other components and contact opportunities among humans bridge the gap between internet available and nonavailable area. In this paper, we have proposed a new routing approach which utilizes both spatial and temporal attributes of user such as probability to meet a particular location and remaining intercontact time between two nodes to select better relay nodes. Generally, users visit different locations such as sports stadium and mall, with varying probability. Users with similar interest form group, and each user has different intercontact time with other users according to their point of interest and visiting pattern. By utilizing multiattributes, different forwarding strategies have been devised for both inter and intragroup routing. The proposed work “point of interest (PoI)‐based routing” is implemented in Opportunistic Network Environment simulator, and the performance is analysed in terms of delivery rate, latency, overhead, goodput, and energy consumed. The simulation results show that PoI diminishes 23% of overhead and yields 24% improvement in goodput over the state‐of‐the‐art protocol. Thus, the simulation results reveal that our proposed work provides the balance between routing performance and resource consumption.     

Energy‐efficient data transmission technique for wireless sensor networks based on DSC and virtual MIMO

In a wireless sensor network (WSN), the data transmission technique based on the cooperative multiple‐input multiple‐output (CMIMO) scheme reduces the energy consumption of sensor nodes quite effectively by utilizing the space‐time block coding scheme. However, in networks with high node density, the scheme is ineffective due to the high degree of correlated data. Therefore, to enhance the energy efficiency in high node density WSNs, we implemented the distributed source coding (DSC) with the virtual multiple‐input multiple‐output (MIMO) data transmission technique in the WSNs. The DSC‐MIMO first compresses redundant source data using the DSC and then sends it to a virtual MIMO link. The results reveal that, in the DSC‐MIMO scheme, energy consumption is lower than that in the CMIMO technique; it is also lower in the DSC single‐input single‐output (SISO) scheme, compared to that in the SISO technique at various code rates, compression rates, and training overhead factors. The results also indicate that the energy consumption per bit is directly proportional to the velocity and training overhead factor in all the energy saving schemes.     

Correction to: Similar Feed-forward Loop Crosstalk Patterns may Impact Robust Information Transport Across E. coli and S. Cerevisiae Transcriptional Networks

Mobile Networks and Applications - The original version of this article unfortunately contained a mistake in the author group section. Author Preetam Ghosh’s given name was incorrectly...